ice40/primitives/sb_ff/sb_ff.model.xml

<!-- set: ai sw=1 ts=1 sta et -->
 <models>
  <!-- module SB_DFF (output Q, input C, D); -->
  <model name="SB_DFF">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFE (output Q, input C, E, D); -->
  <model name="SB_DFFE">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFER (output Q, input C, E, R, D); -->
  <model name="SB_DFFER">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFES (output Q, input C, E, S, D); -->
  <model name="SB_DFFES">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
 </model>

  <!-- module SB_DFFESR (output Q, input C, E, R, D); -->
  <model name="SB_DFFESR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFESS (output Q, input C, E, S, D); -->
  <model name="SB_DFFESS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFR (output Q, input C, R, D); -->
  <model name="SB_DFFR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFS (output Q, input C, S, D); -->
  <model name="SB_DFFS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFSR (output Q, input C, R, D); -->
  <model name="SB_DFFSR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFSS (output Q, input C, S, D); -->
  <model name="SB_DFFSS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFN (output Q, input C, D); -->
  <model name="SB_DFFN">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNE (output Q, input C, E, D); -->
  <model name="SB_DFFNE">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNER (output Q, input C, E, R, D); -->
  <model name="SB_DFFNER">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNES (output Q, input C, E, R, D); -->
  <model name="SB_DFFNES">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
 </model>

  <!-- module SB_DFFNESR (output Q, input C, E, R, D); -->
  <model name="SB_DFFNESR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNESS (output Q, input C, E, S, D); -->
  <model name="SB_DFFNESS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="E" clock="C" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNR (output Q, input C, R, D); -->
  <model name="SB_DFFNR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNS (output Q, input C, S, D); -->
  <model name="SB_DFFNS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNSR (output Q, input C, R, D); -->
  <model name="SB_DFFNSR">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="R" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

  <!-- module SB_DFFNSS (output Q, input C, S, D); -->
  <model name="SB_DFFNSS">
   <input_ports>
    <port name="C" is_clock="1" />
    <port name="S" clock="C" />
    <port name="D" clock="C" />
   </input_ports>
   <output_ports>
    <port name="Q" clock="C" />
   </output_ports>
  </model>

 </models>