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| <section id="supported-architectures"> |
| <h1 id="status--page-root">Supported Architectures<a class="headerlink" href="#status--page-root" title="Link to this heading">¶</a></h1> |
| <ul class="simple"> |
| <li><p><a class="reference external" href="https://www.xilinx.com/video/fpga/7-series-fpga-overview.html">Xilinx 7-Series</a>: |
| the most popular Xilinx FPGA family.</p></li> |
| <li><p><a class="reference external" href="https://www.latticesemi.com/iCE40">Lattice ice40</a>: |
| world’s smallest FPGAs for mobile devices.</p></li> |
| <li><p><a class="reference external" href="https://www.latticesemi.com/Products/FPGAandCPLD/ECP5">Lattice ecp5</a>: |
| low cost FPGAs with high performance features.</p></li> |
| <li><p><a class="reference external" href="https://www.quicklogic.com/products/eos-s3/">QuickLogic EOS S3</a>: |
| FPGA + CPU sensor processing platform.</p></li> |
| <li><p><a class="reference external" href="https://www.quicklogic.com/products/efpga/efpga-ip-software/">QuickLogic QLF K4N8</a>: |
| a 24x24 eFPGA with 6144 flip-flops, 4608 LUT4s, adder and shift-register support.</p></li> |
| <li><p>Do you want to add more? <a class="reference internal" href="community.html#contributing"><span class="std std-ref">Help us!</span></a></p></li> |
| </ul> |
| <section id="bitstream-documentation"> |
| <h2 id="bitstream-documentation">Bitstream documentation<a class="headerlink" href="#bitstream-documentation" title="Link to this heading">¶</a></h2> |
| <table> |
| <thead> |
| <tr class="row-odd"><th class="head"></th> |
| <th class="head"><p>Project Icestorm</p></th> |
| <th class="head"><p>Project Trellis</p></th> |
| <th class="head"><p>Project X-Ray</p></th> |
| <th class="head"><p>QuickLogic Database</p></th> |
| </tr> |
| </thead> |
| <tbody> |
| <tr class="row-even"><td><p>[Basic Tiles] Logic</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-odd"><td><p>[Basic Tiles] Block RAM</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Partial</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-even"><td><p>[Advanced Tiles] DSP</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Partial</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-odd"><td><p>[Advanced Tiles] Hard Blocks</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Partial</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-even"><td><p>[Advanced Tiles] Clock Tiles</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-odd"><td><p>[Advanced Tiles] IO Tiles</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-even"><td><p>[Routing] Logic</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| <tr class="row-odd"><td><p>[Routing] Clock</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| <td><p>Yes</p></td> |
| </tr> |
| </tbody> |
| </table> |
| </section> |
| <section id="boards"> |
| <h2 id="boards">Boards<a class="headerlink" href="#boards" title="Link to this heading">¶</a></h2> |
| <p>See <a class="reference external" href="https://f4pga.org/#boards">f4pga.org: Supported boards</a>.</p> |
| </section> |
| </section> |
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