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<section id="understanding-the-deprecated-flow">
<span id="understanding"></span><h1 id="f4pga-deprecated--page-root">Understanding the (deprecated) flow<a class="headerlink" href="#f4pga-deprecated--page-root" title="Link to this heading"></a></h1>
<div class="admonition important">
<p class="admonition-title">Important</p>
<p>This section describes the usage of the now deprecated <code class="docutils literal notranslate"><span class="pre">symbiflow_*</span></code> entrypoints/wrappers.
It is provided for backwards compatibility, so that users of the <em>old</em> flow can keep using it.
However, it is recommended for new users to use the approach explained in <a class="reference internal" href="index.html#pyf4pga"><span class="std std-ref">Overview</span></a>.</p>
</div>
<p>This section provides valuable information on how each of the commands used to compile and build
designs in F4PGA work. It is especially helpful for debugging or for using methods
other than a makefile to build your designs, such as a bash or python script.</p>
<p>The following describes the commands for running each of the steps for a full design flow
(synthesis, place and route, and generate bitstream) as well as giving a description of the most
common flags for those commands. If you would like a more detailed break down of how the design
flow for F4PGA works take a look at the <a class="reference internal" href="../flows/index.html#flows"><span class="std std-ref">Design Flows section</span></a>.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Files created by synthesis, implementation, and bitstream generation will be dumped into
the directory from which the command is run by default. To keep all of the files generated by
the toolchain separate from your design files, you might consider running the toolchain
commands in a separate directory from your design files.</p>
</div>
<section id="synthesis">
<h2 id="synthesis">Synthesis<a class="headerlink" href="#synthesis" title="Link to this heading"></a></h2>
<p>To synthesize your designs run the <code class="docutils literal notranslate"><span class="pre">symbiflow_synth</span></code> command. The command has the following
flags:</p>
<table id="id1">
<caption><span class="caption-number">Table 1 </span><span class="caption-text">symbiflow_synth</span><a class="headerlink" href="#id1" title="Link to this table"></a></caption>
<thead>
<tr class="row-odd"><th class="head"><p>Flag</p></th>
<th class="head"><p>Argument</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>-t</p></td>
<td><p>Defines the name for the top level module</p></td>
</tr>
<tr class="row-odd"><td><p>-v</p></td>
<td><p>A list of paths to verilog files for the design</p></td>
</tr>
<tr class="row-even"><td><p>-d</p></td>
<td><p>FPGA family (i.e. artix7 or zynq7)</p></td>
</tr>
<tr class="row-odd"><td><p>-p</p></td>
<td><p>The part number for the FPGA (i.e xc7a35tcsg324-1)</p></td>
</tr>
<tr class="row-even"><td><p>-x</p></td>
<td><p>Optional command: path to xdc files for design</p></td>
</tr>
</tbody>
</table>
<p>An example of how to run synthesis on a design containing two separate
verilog HDL files is below. The design is built for a basys3 board which comes from the artix7
family and uses the xc7a35tcpg236-1 chip.</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>symbiflow_synth<span class="w"> </span>-t<span class="w"> </span>top<span class="w"> </span>-v<span class="w"> </span>example.v<span class="w"> </span>top_example.v<span class="w"> </span>-d<span class="w"> </span>artix7<span class="w"> </span>-p<span class="w"> </span>xc7a35tcpg236-1<span class="w"> </span>-x<span class="w"> </span>design_constraint.xdc
</pre></div>
</div>
<p>Synthesis is carried out using the Yosys open source tool. <code class="docutils literal notranslate"><span class="pre">symbiflow_synth</span></code> generates
an .eblif file, a few verilog netlists that describe the gate level design for your project, and a log
file. For more information on Yosys and its relation to F4PGA go to <a class="reference internal" href="../flows/f4pga.html#flows-f4pga-yosys"><span class="std std-ref">Yosys</span></a>.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>The build files generated by the toolchain (for example .eblif from synthesis, .net from
packing, .bit from generate bitstream) are named using the top module specified in
symbiflow_synth. For example if you specified <code class="docutils literal notranslate"><span class="pre">switch_top</span></code> as the top level module name
during synthesis using the <code class="docutils literal notranslate"><span class="pre">-t</span></code> flag, the build files generated by the toolchain would be
named switch_top.eblif, switch_top.net, etc.</p>
</div>
</section>
<section id="place-and-route">
<h2 id="place-and-route">Place and Route<a class="headerlink" href="#place-and-route" title="Link to this heading"></a></h2>
<p>The three steps for implementing a design are internally handled by the open source VPR
(Versatile Place and Route) tool. For more information go to <a class="reference external" href="https://docs.verilogtorouting.org/en/latest/vpr/">VPR ➚</a>.</p>
<section id="pack">
<h3 id="pack">Pack<a class="headerlink" href="#pack" title="Link to this heading"></a></h3>
<p>Packing is run by the <code class="docutils literal notranslate"><span class="pre">symbiflow_pack</span></code> command and generates several files containing
a pin usage report, a timing report, a log file, and a netlist. The various flags for the
pack command are as follows:</p>
<table id="id2">
<caption><span class="caption-number">Table 2 </span><span class="caption-text">symbiflow_pack</span><a class="headerlink" href="#id2" title="Link to this table"></a></caption>
<thead>
<tr class="row-odd"><th class="head"><p>Flag</p></th>
<th class="head"><p>Argument</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>-e</p></td>
<td><p>Path to .eblif file generated by synthesis</p></td>
</tr>
<tr class="row-odd"><td><p>-d</p></td>
<td><p>Fabric definition for the board (i.e. xc7a100t_test)</p></td>
</tr>
<tr class="row-even"><td><p>-s</p></td>
<td><p>Optional: SDC file path</p></td>
</tr>
</tbody>
</table>
<p>Note that the -d option for this step (defining the fabric definition) is different
from the -d from synthesis (defining the FPGA family).</p>
<p>The following example runs packing on the basys3 board:</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>symbiflow_pack<span class="w"> </span>-e<span class="w"> </span>top.eblif<span class="w"> </span>-d<span class="w"> </span>xc7a35t_test
</pre></div>
</div>
</section>
<section id="place">
<h3 id="place">Place<a class="headerlink" href="#place" title="Link to this heading"></a></h3>
<p>Placement generates several files describing the location of design elements
as well as a log file. Placement is run using <code class="docutils literal notranslate"><span class="pre">symbiflow_place</span></code> which utilizes
the following flags:</p>
<table id="id3">
<caption><span class="caption-number">Table 3 </span><span class="caption-text">symbiflow_place</span><a class="headerlink" href="#id3" title="Link to this table"></a></caption>
<thead>
<tr class="row-odd"><th class="head"><p>Flag</p></th>
<th class="head"><p>Argument</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>-e</p></td>
<td><p>Path to .eblif file generated by synthesis</p></td>
</tr>
<tr class="row-odd"><td><p>-d</p></td>
<td><p>Fabric definition (xc7a50t_test)</p></td>
</tr>
<tr class="row-even"><td><p>-p</p></td>
<td><p>Optional: PCF file path</p></td>
</tr>
<tr class="row-odd"><td><p>-n</p></td>
<td><p>Path to the .net file generated by pack step</p></td>
</tr>
<tr class="row-even"><td><p>-P</p></td>
<td><p>The part number for the FPGA (i.e xc7a35tcsg324-1)</p></td>
</tr>
<tr class="row-odd"><td><p>-s</p></td>
<td><p>Optional: SDC file path</p></td>
</tr>
</tbody>
</table>
<p>For the basys3:</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>symbiflow_pack<span class="w"> </span>-e<span class="w"> </span>top.eblif<span class="w"> </span>-d<span class="w"> </span>xc7a35t_test<span class="w"> </span>-p<span class="w"> </span>design.pcf<span class="w"> </span>-n<span class="w"> </span>top.net<span class="w"> </span>-P<span class="w"> </span>xc7a35tcpg236-1<span class="w"> </span>-s<span class="w"> </span>design.sdc
</pre></div>
</div>
</section>
<section id="route">
<h3 id="route">Route<a class="headerlink" href="#route" title="Link to this heading"></a></h3>
<p>Routing produces several timing reports as well as a post routing netlist and log file.
<code class="docutils literal notranslate"><span class="pre">symbiflow_route</span></code> uses the -e, -d, and the optional -s flags. The arguments for these flags
are the same as in the placement step (.eblif, fabric definition, and SDC file path respectively).
The following is an example:</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>symbiflow_route<span class="w"> </span>-e<span class="w"> </span>top.eblif<span class="w"> </span>-d<span class="w"> </span>xc7a35t_test<span class="w"> </span>-s<span class="w"> </span>design.sdc
</pre></div>
</div>
</section>
</section>
<section id="generating-bitstream">
<h2 id="generating-bitstream">Generating Bitstream<a class="headerlink" href="#generating-bitstream" title="Link to this heading"></a></h2>
<p>Generating the bitstream consists of two steps. First, run <code class="docutils literal notranslate"><span class="pre">symbiflow_write_fasm</span></code> to generate
the .fasm file used to create the bitstream. <code class="docutils literal notranslate"><span class="pre">symbiflow_write_fasm</span></code> uses the -e and -d flags
with the same arguments as the placing and routing steps (.eblif path, and fabric definition).
Second, run <code class="docutils literal notranslate"><span class="pre">symbiflow_write_bitstream</span></code> which has the following flags:</p>
<table id="id4">
<caption><span class="caption-number">Table 4 </span><span class="caption-text">symbiflow_write_bitstream</span><a class="headerlink" href="#id4" title="Link to this table"></a></caption>
<thead>
<tr class="row-odd"><th class="head"><p>Flag</p></th>
<th class="head"><p>Argument</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>-d</p></td>
<td><p>FPGA family (i.e. artix7 or zynq7)</p></td>
</tr>
<tr class="row-odd"><td><p>-f</p></td>
<td><p>The path to the .fasm file generated in by write_fasm</p></td>
</tr>
<tr class="row-even"><td><p>-p</p></td>
<td><p>The FPGA part number (i.e xc7a35tcsg324-1)</p></td>
</tr>
<tr class="row-odd"><td><p>-b</p></td>
<td><p>Name of the file to write the bitstream to</p></td>
</tr>
</tbody>
</table>
<p>Notice that the specification for the part number is a lowercase <code class="docutils literal notranslate"><span class="pre">-p</span></code> instead of a capital
<code class="docutils literal notranslate"><span class="pre">-P</span></code> as in the placement step. Also note that the <code class="docutils literal notranslate"><span class="pre">-d</span></code> in write_bitstream defines the FPGA
family instead of the fabric as in the write_fasm step.</p>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>If you change the name of the output for your bitstream to something other than top.bit then the
openFPGALoader command used in the examples would need to change too. For example if I used
<code class="docutils literal notranslate"><span class="pre">-b</span> <span class="pre">my_module_top</span></code> in symbiflow_write_bitstream then my openFPGALoader command would change to:</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>openFPGALoader<span class="w"> </span>-b<span class="w"> </span><span class="nv">$OFL_BOARD</span><span class="w"> </span>my_module_top.bit
</pre></div>
</div>
<p>Note that the only part of the command that changes is “&lt;top module name&gt;.bit;”</p>
</div>
<p>The following example generates a bitstream file named example.bit for the basys3 board:</p>
<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>symbiflow_write_fasm<span class="w"> </span>-e<span class="w"> </span>top.eblif<span class="w"> </span>-d<span class="w"> </span>xc7a50t_test
symbiflow_write_bitstream<span class="w"> </span>-d<span class="w"> </span>artix7<span class="w"> </span>-f<span class="w"> </span>top.fasm<span class="w"> </span>-p<span class="w"> </span>xc7a35tcpg236-1<span class="w"> </span>-b<span class="w"> </span>example.bit
</pre></div>
</div>
</section>
</section>
</article>
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