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<span class="label"><span class="fn-bracket">[</span>R23<span class="fn-bracket">]</span></span>
<p>Clifford Wolf and Johann Glaser. A Free Verilog Synthesis Suite. In <em>Proceedings of Austrochip 2013</em>. 2013. URL: <a class="reference external" href="https://yosyshq.net/yosys/">https://yosyshq.net/yosys/</a>.</p>
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