| commit | 5b95deb96395f35c7cadedd548d615293bcfd897 | [log] [tgz] |
|---|---|---|
| author | Alain Dargelas <5085492+alainmarcel@users.noreply.github.com> | Fri Nov 22 07:01:54 2019 -0800 |
| committer | GitHub <noreply@github.com> | Fri Nov 22 07:01:54 2019 -0800 |
| tree | 517c9d241a051acf9aadd83b273dcdc0539d8337 | |
| parent | cad7aea7666a37c932253b201d4ca8fdc0cf7e24 [diff] | |
| parent | 509d74c8274136d651c20786720d09291a7e6fc0 [diff] |
Merge pull request #104 from alainmarcel/alainmarcel-patch-1 README
System Verilog 2017 Pre-processor, Parser
This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.
Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models.
This project is open to contributions from any users! From the commercial vendor to the Verilog enthousiast, all are welcome.
INSTALLmake make install (/usr/local/bin and /usr/local/lib/surelog by default, use DESTDIR= for alternative locations)
For more build/test options and system requirements for building see src/README file.
The executable is located here (If not installed in:
STANDARD VERILOG COMMAND LINE:
FLOWS OPTIONS:
TRACES OPTIONS:
OUTPUT OPTIONS:
RETURN CODE