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foss-fpga-tools
/
third_party
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Surelog
/
14189593b2851f86e27e0604e4a37a0d9629aa5c
/
.
/
src
/
Testcases
/
YosysTests
/
simple
/
scripts
/
design_import.ys
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read_verilog
../
top
.
v
proc
design
-
save top
design
-
import
top
write_verilog synth
.
v
