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1b0062119887da734c600d091a65c037f5fafa7d
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SVIncCompil
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Testcases
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YosysTests
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regression
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scripts
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issue_00865.ys
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read_verilog
../
top
.
v
write_verilog temp
.
v
proc
opt
fsm
opt
memory
opt
synth_xilinx
-
top tc
select
-
assert
-
count
12
t
:
FDRE
