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foss-fpga-tools
/
third_party
/
Surelog
/
1c596881d1a7fc4baa7972b1f16b2e3d461aa200
/
.
/
src
/
Testcases
/
YosysTestSuite
/
rpc
/
design.v
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module
top
(
input
[
3
:
0
]
i
,
output
[
3
:
0
]
o
);
python_inv
#(
.
width
(
4
)
)
inv
(
.
i
(
i
),
.
o
(
o
),
);
endmodule
