| read_verilog -sv ../top.v | |
| hierarchy -top top | |
| proc | |
| write_btor btor.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| synth -top top | |
| write_btor btor1.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| proc_prune | |
| proc_init | |
| proc_mux | |
| proc_dff | |
| write_btor btor2.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| synth | |
| abc | |
| write_btor btor3.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| synth -top top | |
| abc -g AND,XOR,NOR | |
| write_btor btor4.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| synth -top top | |
| abc -g ANDNOT,ORNOT | |
| write_btor btor5.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| synth -top top | |
| abc -g cmos3 | |
| write_btor btor6.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| abc -g AOI4 | |
| synth -top top | |
| write_btor btor7.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| abc -g OAI4 | |
| synth -top top | |
| write_btor btor8.btor | |
| design -reset | |
| read_verilog -sv ../top.v | |
| aigmap | |
| proc | |
| write_btor btor9.btor | |
| synth -top top | |
| write_btor btor10.btor | |
| design -reset | |
| read_verilog -sv ../top_clean.v | |
| synth -top top | |
| write_verilog synth.v |