SVIncCompil/Testcases/YosysTests/regression/issue_00644/top.v - third_party/Surelog - Git at Google

 module top(clk, in, out);
     parameter DEPTH=10;
     input wire clk, in;
     output reg out;


     always @(posedge clk)
 		assert($changed(in) == (in != $past(in)));

 endmodule
	module top(clk, in, out);
	parameter DEPTH=10;
	input wire clk, in;
	output reg out;


	always @(posedge clk)
	assert($changed(in) == (in != $past(in)));

	endmodule