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SVIncCompil
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Testcases
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chapter-6
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6.5--variable_redeclare.sv
blob: 7d821fc6ffce53a3b063e89c7a67d6485c9a8986 [
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/*
:name: variable_redeclare
:description: Variable redeclaration tests
:should_fail: 1
:tags: 6.5
:type: simulation
*/
module
top
();
reg v
;
wire v
;
endmodule