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foss-fpga-tools
/
third_party
/
Surelog
/
2b38692156ff2742b1c4c94d3b93df97f2145e0c
/
.
/
SVIncCompil
/
Testcases
/
YosysTestSuite
/
errors
/
syntax_err09.v
blob: 1e472eb94ae9d0283aecd18824b50d5e458ea338 [
file
]
module
a
(
input wire x
=
1
'b0);
endmodule
