SVIncCompil/Testcases/YosysTestSuite/lut/map_or.v - third_party/Surelog - Git at Google

 module top(...);
     input a, b;
     output y;
     assign y = a|b;
 endmodule
	module top(...);
	input a, b;
	output y;
	assign y = a\|b;
	endmodule