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foss-fpga-tools
/
third_party
/
Surelog
/
2b38692156ff2742b1c4c94d3b93df97f2145e0c
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01193
/
top.v
blob: 25fc6e76494237a26ad42b7d0de8aa4e38b18f27 [
file
]
module
test
(
input e
,
a
,
output reg b
);
always_comb
if
(
e
)
b
=
a
;
endmodule
