Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
2b38692156ff2742b1c4c94d3b93df97f2145e0c
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_wire_attr.ys
blob: a39654a59c3aa6bba4f219e7084c1ca27ed11ec9 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
extract
-
map
../
top
.
v
-
wire_attr attr
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v