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foss-fpga-tools / third_party / Surelog / 356a4bf2123fc606ca19fbed9b9c535f149fdec5 / . / SVIncCompil / Testcases / YosysTests / architecture / synth_xilinx_srl
tree: 15ed447fc12cc14480b7804987010aa827100b5a [path history] [tgz]
  1. generate.py
  2. lfsr_area.py
  3. multiclock.v
  4. multiclock_var_len.v
  5. multien.v
  6. multien_var_len.v
  7. neg_clk_no_enable_with_init_with_inferred_N_width.v
  8. neg_clk_no_enable_with_init_with_inferred_with_reset.v
  9. neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v
  10. pos_clk_no_enable_no_init_not_inferred_N_width.v
  11. pos_clk_no_enable_no_init_not_inferred_with_reset.v
  12. pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v
  13. rotate_3.v
  14. rotate_3_fdre.v
  15. rotate_3_var_len.v
  16. rotate_7_fdre_param.v
  17. rotate_7_fdre_reset.v
  18. run-test.sh
  19. sr_fixed_length_other_users_port.v
  20. sr_fixed_length_other_users_xor.v
  21. sr_var_length_other_users_port.v
  22. sr_var_length_other_users_xor.v
  23. test17a.v
  24. test17b.v
  25. test17c.v
  26. test17d.v
  27. test17e.v
  28. test20.v
  29. test21a.v
  30. test21b.v
  31. ug901a.v
  32. ug901b.v
  33. ug901c.v