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foss-fpga-tools / third_party / Surelog / 356a4bf2123fc606ca19fbed9b9c535f149fdec5 / . / SVIncCompil / Testcases / YosysTests / architecture / xilinx_ug901_synthesis_examples
tree: 301da1e9a9a5153b2501358d6ea2e23978898aab [path history] [tgz]
  1. asym_ram_sdp_read_wider.v
  2. asym_ram_sdp_write_wider.v
  3. asym_ram_tdp_read_first.v
  4. asym_ram_tdp_write_first.v
  5. black_box_1.v
  6. bytewrite_ram_1b.v
  7. bytewrite_tdp_ram_nc.v
  8. bytewrite_tdp_ram_readfirst2.v
  9. bytewrite_tdp_ram_rf.v
  10. bytewrite_tdp_ram_wf.v
  11. cmacc.v
  12. cmult.v
  13. dynamic_shift_registers_1.v
  14. dynpreaddmultadd.v
  15. fsm_1.v
  16. latches.v
  17. macc.v
  18. mult_unsigned.v
  19. presubmult.v
  20. ram_simple_dual_one_clock.v
  21. ram_simple_dual_two_clocks.v
  22. rams_dist.v
  23. rams_init_file.data
  24. rams_init_file.v
  25. rams_pipeline.v
  26. rams_sp_nc.v
  27. rams_sp_rf.v
  28. rams_sp_rf_rst.v
  29. rams_sp_rom.v
  30. rams_sp_rom_1.v
  31. rams_sp_wf.v
  32. rams_tdp_rf_rf.v
  33. registers_1.v
  34. sfir_shifter.v
  35. shift_registers_0.v
  36. shift_registers_1.v
  37. squarediffmacc.v
  38. squarediffmult.v
  39. top_mux.v
  40. tristates_1.v
  41. tristates_2.v
  42. xilinx_ultraram_single_port_no_change.v
  43. xilinx_ultraram_single_port_read_first.v
  44. xilinx_ultraram_single_port_write_first.v