SVIncCompil/Testcases/Google/chapter-6/6.12--real_bit_select.sv - third_party/Surelog - Git at Google

 /*
 :name: real_idx
 :description: real indexing tests
 :should_fail: 1
 :tags: 6.12
 */
 module top();
 	real a = 0.5;
 	wire b;

 	assign b = a[2];
 endmodule
	/*
	:name: real_idx
	:description: real indexing tests
	:should_fail: 1
	:tags: 6.12
	*/
	module top();
	real a = 0.5;
	wire b;

	assign b = a[2];
	endmodule