SVIncCompil/Testcases/Google/chapter-6/6.6.8--interconnect.sv.log

********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

Copyright (c) 2017-2019 ACE Cloud,
Authorized used only.

VERSION: 0.05
BUILT  : Oct  1 2019
DATE   : 2019-10-01.09:14:27
COMMAND: tests/chapter-6/6.6.8--interconnect.sv -writepp -parse -mt max -l tests/chapter-6/6.6.8--interconnect.sv.log -nostdout -verbose +define+DIGITS=10 +define+WIDTH=2

[INFO :CM0023] Creating log file tests/chapter-6/6.6.8--interconnect.sv.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :PP0122] Preprocessing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[INFO :PP0122] Preprocessing source file "tests/chapter-6/6.6.8--interconnect.sv".

[INFO :PA0201] Parsing source file "/home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv".

[INFO :PA0201] Parsing source file "tests/chapter-6/6.6.8--interconnect.sv".

[WARNI:PA0205] tests/chapter-6/6.6.8--interconnect.sv, line 7: No timescale set for "top".

[WARNI:PA0205] tests/chapter-6/6.6.8--interconnect.sv, line 14: No timescale set for "mod_i".

[WARNI:PA0205] tests/chapter-6/6.6.8--interconnect.sv, line 18: No timescale set for "mod_o".

[INFO :CP0300] Compilation...

[INFO :CP0303] tests/chapter-6/6.6.8--interconnect.sv, line 14: Compile module "work@mod_i".

[INFO :CP0303] tests/chapter-6/6.6.8--interconnect.sv, line 18: Compile module "work@mod_o".

[INFO :CP0303] tests/chapter-6/6.6.8--interconnect.sv, line 7: Compile module "work@top".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 4: Compile class "work@mailbox".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 58: Compile class "work@semaphore".

[INFO :CP0302] /home/alain/surelog/SVIncCompil/dist/Release/GNU-Linux/../sv/builtin.sv, line 33: Compile class "work@process".

[NOTE :CP0309] tests/chapter-6/6.6.8--interconnect.sv, line 14: Implicit port type (wire) for "in".

[NOTE :CP0309] tests/chapter-6/6.6.8--interconnect.sv, line 18: Implicit port type (wire) for "out".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] tests/chapter-6/6.6.8--interconnect.sv, line 7: Top level module "work@top".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 3.

[NOTE :EL0511] Nb leaf instances: 2.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 3
[   NOTE] : 7

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************