| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| Copyright (c) 2017-2019 ACE Cloud, |
| Authorized used only. |
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| VERSION: 0.05 |
| BUILT : Nov 3 2019 |
| DATE : 2019-11-03.21:44:13 |
| COMMAND: -writepp -parse -mt max -nopython -fileunit cache/synth.v rtl/sasc_brg.v rtl/sasc_fifo4.v rtl/sasc_top.v rtl/timescale.v +incdir+. -nobuiltin -nocache |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [ERROR:PP0101] rtl/sasc_brg.v:66 Cannot open include file "timescale.v". |
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| [ERROR:PP0101] rtl/sasc_fifo4.v:60 Cannot open include file "timescale.v". |
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| [ERROR:PP0101] rtl/sasc_top.v:62 Cannot open include file "timescale.v". |
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| [WARNI:PA0205] cache/synth.v:1 No timescale set for "sasc_fifo4". |
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| [WARNI:PA0205] cache/synth.v:282 No timescale set for "sasc_top". |
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| [WARNI:PA0205] timescale.v:22 No timescale set for "sasc_brg". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:282 Compile module "work@sasc_top". |
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| [INFO :CP0303] timescale.v:22 Compile module "work@sasc_brg". |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@sasc_fifo4". |
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| [NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout", |
| there are 2 more instances of this message. |
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| [NOTE :CP0309] cache/synth.v:282 Implicit port type (wire) for "dout_o", |
| there are 2 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] cache/synth.v:282 Top level module "work@sasc_top". |
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| [NOTE :EL0503] timescale.v:22 Top level module "work@sasc_brg". |
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| [NOTE :EL0504] Multiple top level modules in design. |
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| [NOTE :EL0508] Nb Top level modules: 2. |
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| [NOTE :EL0509] Max instance depth: 2. |
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| [NOTE :EL0510] Nb instances: 4. |
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| [NOTE :EL0511] Nb leaf instances: 3. |
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| [ FATAL] : 0 |
| [ ERROR] : 3 |
| [WARNING] : 3 |
| [ NOTE] : 9 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
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