| |
| /-----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \-----------------------------------------------------------------------------/ |
| |
| |
| -- Executing script file `scripts/synth.ys' -- |
| |
| 1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/fifo4.v |
| Parsing Verilog input from `rtl/fifo4.v' to AST representation. |
| Warning: Found one of those horrible `synopsys translate_off' comments. |
| It is strongly suggested to use `ifdef constructs instead! |
| Generating RTLIL representation for module `\fifo4'. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/simple_spi_top.v |
| Parsing Verilog input from `rtl/simple_spi_top.v' to AST representation. |
| Warning: Found one of those horrible `synopsys translate_off' comments. |
| It is strongly suggested to use `ifdef constructs instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Generating RTLIL representation for module `\simple_spi_top'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing HIERARCHY pass (managing design hierarchy). |
| Full command line: hierarchy -top simple_spi_top |
| Top module: \simple_spi_top |
| Used module: \fifo4 |
| Removed 0 unused modules. |
| |
| 4. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo4'. |
| Parameter 1 (\dw) = 8 |
| Generating RTLIL representation for module `$paramod\fifo4\dw=8'. |
| |
| 5. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo4'. |
| Parameter 1 (\dw) = 8 |
| Found cached RTLIL representation for module `$paramod\fifo4\dw=8'. |
| Top module: \simple_spi_top |
| Used module: $paramod\fifo4\dw=8 |
| Removing unused module `\fifo4'. |
| Removed 1 unused modules. |
| |
| -- Executing script file `../scripts/generic.ys' -- |
| |
| 6. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 7. Executing PROC pass (convert processes to netlists). |
| |
| 7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed a total of 0 dead cases. |
| |
| 7.3. Executing PROC_ARST pass (detect async resets in processes). |
| Found async reset \rst in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:105$90'. |
| Found async reset \rst in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:95$86'. |
| Found async reset \rst_i in `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| Found async reset \rst_i in `\simple_spi_top.$proc$rtl/simple_spi_top.v:156$39'. |
| |
| 7.4. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:105$90'. |
| creating decoder for signal `$0\rp[1:0]'. |
| Creating decoders for process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| creating decoder for signal `$0$memwr$\mem$rtl/fifo4.v:119$85_ADDR[1:0]'. |
| creating decoder for signal `$0$memwr$\mem$rtl/fifo4.v:119$85_DATA[7:0]'. |
| creating decoder for signal `$0$memwr$\mem$rtl/fifo4.v:119$85_EN[0:0]'. |
| Creating decoders for process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:126$100'. |
| creating decoder for signal `$0\gb[0:0]'. |
| Creating decoders for process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:95$86'. |
| creating decoder for signal `$0\wp[1:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| creating decoder for signal `$0\spcr[7:0]'. |
| creating decoder for signal `$0\sper[7:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:144$33'. |
| creating decoder for signal `$0\dat_o[7:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:156$39'. |
| creating decoder for signal `$0\ack_o[0:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:181$45'. |
| creating decoder for signal `$0\spif[0:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:188$51'. |
| creating decoder for signal `$0\wcol[0:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:204$57'. |
| creating decoder for signal `$0\inta_o[0:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:236$61'. |
| creating decoder for signal `$0\clkcnt[11:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| creating decoder for signal `$0\bcnt[2:0]'. |
| creating decoder for signal `$0\rfwe[0:0]'. |
| creating decoder for signal `$0\sck_o[0:0]'. |
| creating decoder for signal `$0\state[1:0]'. |
| creating decoder for signal `$0\treg[7:0]'. |
| creating decoder for signal `$0\wfre[0:0]'. |
| Creating decoders for process `\simple_spi_top.$proc$rtl/simple_spi_top.v:318$78'. |
| creating decoder for signal `$0\tcnt[1:0]'. |
| |
| 7.5. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `$paramod\fifo4\dw=8.\rp' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:105$90'. |
| created $adff cell `$procdff$339' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod\fifo4\dw=8.$memwr$\mem$rtl/fifo4.v:119$85_ADDR' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| created $dff cell `$procdff$340' with positive edge clock. |
| Creating register for signal `$paramod\fifo4\dw=8.$memwr$\mem$rtl/fifo4.v:119$85_DATA' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| created $dff cell `$procdff$341' with positive edge clock. |
| Creating register for signal `$paramod\fifo4\dw=8.$memwr$\mem$rtl/fifo4.v:119$85_EN' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| created $dff cell `$procdff$342' with positive edge clock. |
| Creating register for signal `$paramod\fifo4\dw=8.\gb' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:126$100'. |
| created $dff cell `$procdff$343' with positive edge clock. |
| Creating register for signal `$paramod\fifo4\dw=8.\wp' using process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:95$86'. |
| created $adff cell `$procdff$344' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_top.\spcr' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| created $adff cell `$procdff$345' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_top.\sper' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| created $adff cell `$procdff$346' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_top.\dat_o' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:144$33'. |
| created $dff cell `$procdff$347' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\ack_o' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:156$39'. |
| created $adff cell `$procdff$348' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_top.\spif' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:181$45'. |
| created $dff cell `$procdff$349' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\wcol' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:188$51'. |
| created $dff cell `$procdff$350' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\inta_o' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:204$57'. |
| created $dff cell `$procdff$351' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\clkcnt' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:236$61'. |
| created $dff cell `$procdff$352' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\bcnt' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$353' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\rfwe' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$354' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\sck_o' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$355' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\state' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$356' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\treg' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$357' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\wfre' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| created $dff cell `$procdff$358' with positive edge clock. |
| Creating register for signal `\simple_spi_top.\tcnt' using process `\simple_spi_top.$proc$rtl/simple_spi_top.v:318$78'. |
| created $dff cell `$procdff$359' with positive edge clock. |
| |
| 7.6. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 3 empty switches in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:105$90'. |
| Removing empty process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:105$90'. |
| Found and cleaned up 1 empty switch in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| Removing empty process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:118$94'. |
| Found and cleaned up 4 empty switches in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:126$100'. |
| Removing empty process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:126$100'. |
| Found and cleaned up 3 empty switches in `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:95$86'. |
| Removing empty process `$paramod\fifo4\dw=8.$proc$rtl/fifo4.v:95$86'. |
| Found and cleaned up 4 empty switches in `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:124$23'. |
| Found and cleaned up 1 empty switch in `\simple_spi_top.$proc$rtl/simple_spi_top.v:144$33'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:144$33'. |
| Found and cleaned up 1 empty switch in `\simple_spi_top.$proc$rtl/simple_spi_top.v:156$39'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:156$39'. |
| Found and cleaned up 1 empty switch in `\simple_spi_top.$proc$rtl/simple_spi_top.v:181$45'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:181$45'. |
| Found and cleaned up 1 empty switch in `\simple_spi_top.$proc$rtl/simple_spi_top.v:188$51'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:188$51'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:204$57'. |
| Found and cleaned up 2 empty switches in `\simple_spi_top.$proc$rtl/simple_spi_top.v:236$61'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:236$61'. |
| Found and cleaned up 7 empty switches in `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:259$69'. |
| Found and cleaned up 3 empty switches in `\simple_spi_top.$proc$rtl/simple_spi_top.v:318$78'. |
| Removing empty process `\simple_spi_top.$proc$rtl/simple_spi_top.v:318$78'. |
| Cleaned up 31 empty switches. |
| |
| 8. Executing OPT pass (performing simple optimizations). |
| |
| 8.1. Optimizing in-memory representation of design. |
| |
| 8.2. Executing OPT_CONST pass (perform const folding). |
| |
| 8.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Cell `$eq$rtl/fifo4.v:123$98' is identical to cell `$eq$rtl/fifo4.v:122$95'. |
| Redirecting output \Y: $eq$rtl/fifo4.v:123$98_Y = $eq$rtl/fifo4.v:122$95_Y |
| Removing $eq cell `$eq$rtl/fifo4.v:123$98' from module `$paramod\fifo4\dw=8'. |
| Cell `$logic_not$rtl/fifo4.v:127$101' is identical to cell `$logic_not$rtl/fifo4.v:106$91'. |
| Redirecting output \Y: $logic_not$rtl/fifo4.v:127$101_Y = $logic_not$rtl/fifo4.v:106$91_Y |
| Removing $logic_not cell `$logic_not$rtl/fifo4.v:127$101' from module `$paramod\fifo4\dw=8'. |
| Cell `$logic_not$rtl/fifo4.v:96$87' is identical to cell `$logic_not$rtl/fifo4.v:106$91'. |
| Redirecting output \Y: $logic_not$rtl/fifo4.v:96$87_Y = $logic_not$rtl/fifo4.v:106$91_Y |
| Removing $logic_not cell `$logic_not$rtl/fifo4.v:96$87' from module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Cell `$eq$rtl/simple_spi_top.v:153$34' is identical to cell `$eq$rtl/simple_spi_top.v:140$28'. |
| Redirecting output \Y: $eq$rtl/simple_spi_top.v:153$34_Y = $eq$rtl/simple_spi_top.v:140$28_Y |
| Removing $eq cell `$eq$rtl/simple_spi_top.v:153$34' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:157$40' is identical to cell `$not$rtl/simple_spi_top.v:125$24'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:157$40_Y = $not$rtl/simple_spi_top.v:125$24_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:157$40' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:189$52' is identical to cell `$not$rtl/simple_spi_top.v:182$46'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:189$52_Y = $not$rtl/simple_spi_top.v:182$46_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:189$52' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:213$59' is identical to cell `$not$rtl/simple_spi_top.v:182$46'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:213$59_Y = $not$rtl/simple_spi_top.v:182$46_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:213$59' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:224$60' is identical to cell `$not$rtl/simple_spi_top.v:182$46'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:224$60_Y = $not$rtl/simple_spi_top.v:182$46_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:224$60' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:260$70' is identical to cell `$not$rtl/simple_spi_top.v:182$46'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:260$70_Y = $not$rtl/simple_spi_top.v:182$46_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:260$70' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:290$73' is identical to cell `$not$rtl/simple_spi_top.v:284$72'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:290$73_Y = $not$rtl/simple_spi_top.v:284$72_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:290$73' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:305$77' is identical to cell `$not$rtl/simple_spi_top.v:284$72'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:305$77_Y = $not$rtl/simple_spi_top.v:284$72_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:305$77' from module `\simple_spi_top'. |
| Cell `$not$rtl/simple_spi_top.v:319$79' is identical to cell `$not$rtl/simple_spi_top.v:182$46'. |
| Redirecting output \Y: $not$rtl/simple_spi_top.v:319$79_Y = $not$rtl/simple_spi_top.v:182$46_Y |
| Removing $not cell `$not$rtl/simple_spi_top.v:319$79' from module `\simple_spi_top'. |
| Cell `$procmux$160_CMP0' is identical to cell `$eq$rtl/simple_spi_top.v:140$28'. |
| Redirecting output \Y: $procmux$160_CMP = $eq$rtl/simple_spi_top.v:140$28_Y |
| Removing $eq cell `$procmux$160_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$162_CMP0' is identical to cell `$eq$rtl/simple_spi_top.v:178$43'. |
| Redirecting output \Y: $procmux$162_CMP = $eq$rtl/simple_spi_top.v:178$43_Y |
| Removing $eq cell `$procmux$162_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$164_CMP0' is identical to cell `$eq$rtl/simple_spi_top.v:132$25'. |
| Redirecting output \Y: $procmux$164_CMP = $eq$rtl/simple_spi_top.v:132$25_Y |
| Removing $eq cell `$procmux$164_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$227_CMP0' is identical to cell `$procmux$205_CMP0'. |
| Redirecting output \Y: $procmux$227_CMP = $procmux$205_CMP |
| Removing $eq cell `$procmux$227_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$231_CMP0' is identical to cell `$procmux$209_CMP0'. |
| Redirecting output \Y: $procmux$231_CMP = $procmux$209_CMP |
| Removing $eq cell `$procmux$231_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$237_CMP0' is identical to cell `$procmux$215_CMP0'. |
| Redirecting output \Y: $procmux$237_CMP = $procmux$215_CMP |
| Removing $eq cell `$procmux$237_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$249_CMP0' is identical to cell `$procmux$205_CMP0'. |
| Redirecting output \Y: $procmux$249_CMP = $procmux$205_CMP |
| Removing $eq cell `$procmux$249_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$254_CMP0' is identical to cell `$procmux$209_CMP0'. |
| Redirecting output \Y: $procmux$254_CMP = $procmux$209_CMP |
| Removing $eq cell `$procmux$254_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$262_CMP0' is identical to cell `$procmux$215_CMP0'. |
| Redirecting output \Y: $procmux$262_CMP = $procmux$215_CMP |
| Removing $eq cell `$procmux$262_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$274_CMP0' is identical to cell `$procmux$205_CMP0'. |
| Redirecting output \Y: $procmux$274_CMP = $procmux$205_CMP |
| Removing $eq cell `$procmux$274_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$279_CMP0' is identical to cell `$procmux$209_CMP0'. |
| Redirecting output \Y: $procmux$279_CMP = $procmux$209_CMP |
| Removing $eq cell `$procmux$279_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$286_CMP0' is identical to cell `$procmux$215_CMP0'. |
| Redirecting output \Y: $procmux$286_CMP = $procmux$215_CMP |
| Removing $eq cell `$procmux$286_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$297_CMP0' is identical to cell `$procmux$205_CMP0'. |
| Redirecting output \Y: $procmux$297_CMP = $procmux$205_CMP |
| Removing $eq cell `$procmux$297_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$301_CMP0' is identical to cell `$procmux$209_CMP0'. |
| Redirecting output \Y: $procmux$301_CMP = $procmux$209_CMP |
| Removing $eq cell `$procmux$301_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$307_CMP0' is identical to cell `$procmux$215_CMP0'. |
| Redirecting output \Y: $procmux$307_CMP = $procmux$215_CMP |
| Removing $eq cell `$procmux$307_CMP0' from module `\simple_spi_top'. |
| Cell `$procmux$326_CMP0' is identical to cell `$procmux$215_CMP0'. |
| Redirecting output \Y: $procmux$326_CMP = $procmux$215_CMP |
| Removing $eq cell `$procmux$326_CMP0' from module `\simple_spi_top'. |
| Cell `$reduce_or$rtl/simple_spi_top.v:256$67' is identical to cell `$reduce_or$rtl/simple_spi_top.v:237$62'. |
| Redirecting output \Y: $reduce_or$rtl/simple_spi_top.v:256$67_Y = $reduce_or$rtl/simple_spi_top.v:237$62_Y |
| Removing $reduce_or cell `$reduce_or$rtl/simple_spi_top.v:256$67' from module `\simple_spi_top'. |
| Cell `$reduce_or$rtl/simple_spi_top.v:327$82' is identical to cell `$reduce_or$rtl/simple_spi_top.v:322$80'. |
| Redirecting output \Y: $reduce_or$rtl/simple_spi_top.v:327$82_Y = $reduce_or$rtl/simple_spi_top.v:322$80_Y |
| Removing $reduce_or cell `$reduce_or$rtl/simple_spi_top.v:327$82' from module `\simple_spi_top'. |
| Cell `$and$rtl/simple_spi_top.v:153$35' is identical to cell `$and$rtl/simple_spi_top.v:140$29'. |
| Redirecting output \Y: $and$rtl/simple_spi_top.v:153$35_Y = $and$rtl/simple_spi_top.v:140$29_Y |
| Removing $and cell `$and$rtl/simple_spi_top.v:153$35' from module `\simple_spi_top'. |
| Cell `$and$rtl/simple_spi_top.v:153$36' is identical to cell `$and$rtl/simple_spi_top.v:140$30'. |
| Redirecting output \Y: $and$rtl/simple_spi_top.v:153$36_Y = $and$rtl/simple_spi_top.v:140$30_Y |
| Removing $and cell `$and$rtl/simple_spi_top.v:153$36' from module `\simple_spi_top'. |
| Removed a total of 32 cells. |
| |
| 8.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 8.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| New ctrl vector for $pmux cell $procmux$204: { $procmux$215_CMP $procmux$205_CMP } |
| New ctrl vector for $pmux cell $procmux$226: $procmux$205_CMP |
| New ctrl vector for $pmux cell $procmux$296: { $procmux$215_CMP $procmux$205_CMP } |
| Performed a total of 3 changes. |
| |
| 8.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 8.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 8.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| removing unused `$add' cell `$add$rtl/fifo4.v:103$89'. |
| removing unused non-port wire \wp_p2. |
| removed 27 unused temporary wires. |
| Finding unused cells or wires in module \simple_spi_top.. |
| removing unused `$not' cell `$not$rtl/simple_spi_top.v:125$24'. |
| removing unused non-port wire \rreg. |
| removed 84 unused temporary wires. |
| |
| 8.9. Executing OPT_CONST pass (perform const folding). |
| |
| 8.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 8.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 8.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 8.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 8.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 8.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| Finding unused cells or wires in module \simple_spi_top.. |
| |
| 8.16. Executing OPT_CONST pass (perform const folding). |
| |
| 8.17. Optimizing in-memory representation of design. |
| |
| 8.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 9. Executing MEMORY pass. |
| |
| 9.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| Checking cell `$memwr$\mem$rtl/fifo4.v:119$104' in module `$paramod\fifo4\dw=8': merged $dff to cell. |
| |
| 9.2. Executing MEMORY_COLLECT pass (generating $mem cells). |
| Collecting $memrd and $memwr for memory `\mem' in module `$paramod\fifo4\dw=8': |
| |
| 9.3. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| Mapping memory cell $mem$\mem$360 in module $paramod\fifo4\dw=8: |
| created 4 $dff cells and 0 static cells of width 8. |
| read interface: 0 $dff and 3 $mux cells. |
| write interface: 4 blocks of $eq, $and and $mux cells. |
| |
| 10. Executing OPT pass (performing simple optimizations). |
| |
| 10.1. Optimizing in-memory representation of design. |
| |
| 10.2. Executing OPT_CONST pass (perform const folding). |
| |
| 10.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 10.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 10.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 10.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 10.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 10.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| removing unused `$dff' cell `$procdff$340'. |
| removing unused `$dff' cell `$procdff$341'. |
| removing unused `$dff' cell `$procdff$342'. |
| removed 11 unused temporary wires. |
| Finding unused cells or wires in module \simple_spi_top.. |
| |
| 10.9. Executing OPT_CONST pass (perform const folding). |
| |
| 10.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 10.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 10.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 10.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 10.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 10.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| Finding unused cells or wires in module \simple_spi_top.. |
| |
| 10.16. Executing OPT_CONST pass (perform const folding). |
| |
| 10.17. Optimizing in-memory representation of design. |
| |
| 10.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 11. Executing TECHMAP pass (map to technology primitives). |
| |
| 11.1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog <stdcells.v> |
| Parsing Verilog input from `<stdcells.v>' to AST representation. |
| Generating RTLIL representation for module `\$not'. |
| Generating RTLIL representation for module `\$pos'. |
| Generating RTLIL representation for module `\$neg'. |
| Generating RTLIL representation for module `\$and'. |
| Generating RTLIL representation for module `\$or'. |
| Generating RTLIL representation for module `\$xor'. |
| Generating RTLIL representation for module `\$xnor'. |
| Generating RTLIL representation for module `\$reduce_and'. |
| Generating RTLIL representation for module `\$reduce_or'. |
| Generating RTLIL representation for module `\$reduce_xor'. |
| Generating RTLIL representation for module `\$reduce_xnor'. |
| Generating RTLIL representation for module `\$reduce_bool'. |
| Generating RTLIL representation for module `\$shift'. |
| Generating RTLIL representation for module `\$shl'. |
| Generating RTLIL representation for module `\$shr'. |
| Generating RTLIL representation for module `\$sshl'. |
| Generating RTLIL representation for module `\$sshr'. |
| Generating RTLIL representation for module `\$fulladd'. |
| Generating RTLIL representation for module `\$alu'. |
| Generating RTLIL representation for module `\$lt'. |
| Generating RTLIL representation for module `\$le'. |
| Generating RTLIL representation for module `\$eq'. |
| Generating RTLIL representation for module `\$ne'. |
| Generating RTLIL representation for module `\$ge'. |
| Generating RTLIL representation for module `\$gt'. |
| Generating RTLIL representation for module `\$add'. |
| Generating RTLIL representation for module `\$sub'. |
| Generating RTLIL representation for module `\$logic_not'. |
| Generating RTLIL representation for module `\$logic_and'. |
| Generating RTLIL representation for module `\$logic_or'. |
| Generating RTLIL representation for module `\$mux'. |
| Generating RTLIL representation for module `\$pmux'. |
| Generating RTLIL representation for module `\$safe_pmux'. |
| Generating RTLIL representation for module `\$dff'. |
| Generating RTLIL representation for module `\$adff'. |
| Successfully finished Verilog frontend. |
| |
| 11.2. Executing AST frontend in derive mode using pre-parsed AST for module `$add'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.3. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.4. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.5. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:122$97' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:123$99' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:131$103' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.6. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.7. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:122$95' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:131$102' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.8. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.9. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$logic_not$rtl/fifo4.v:106$91' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$logic_not$rtl/fifo4.v:122$96' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.10. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=8'. |
| |
| 11.11. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$rdmux[0][0][0]$369' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$rdmux[0][1][0]$372' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$rdmux[0][1][1]$375' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[0][0]$380' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[1][0]$386' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[2][0]$392' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[3][0]$398' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[0][0]$378' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[1][0]$384' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[2][0]$390' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[3][0]$396' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wrmux[0][0]$382' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wrmux[1][0]$388' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wrmux[2][0]$394' using `$paramod$mux\WIDTH=8'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wrmux[3][0]$400' using `$paramod$mux\WIDTH=8'. |
| |
| 11.12. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 11.13. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360[0]$361' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360[1]$363' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360[2]$365' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360[3]$367' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 11.14. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 2 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 2'00 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 11.15. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$procdff$339' using `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 11.16. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 11.17. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$procdff$343' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `$paramod\fifo4\dw=8.$procdff$344' using `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 11.18. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=2'. |
| |
| 11.19. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$procmux$106' using `$paramod$mux\WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$109' using `$paramod$mux\WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$113' using `$paramod$mux\WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$116' using `$paramod$mux\WIDTH=8'. |
| |
| 11.20. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=1'. |
| |
| 11.21. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$procmux$119' using `$paramod$mux\WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$122' using `$paramod$mux\WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$125' using `$paramod$mux\WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$128' using `$paramod$mux\WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$131' using `$paramod$mux\WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$134' using `$paramod$mux\WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$procmux$137' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:120$21' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:121$22' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$29' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$30' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$31' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:141$32' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:153$38' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:160$42' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:178$44' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$48' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$50' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$54' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$56' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:205$58' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$64' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$65' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:327$84' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:132$25' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:135$27' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:140$28' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:178$43' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$logic_not$rtl/simple_spi_top.v:160$41' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.22. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.23. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:153$37' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:182$46' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:185$49' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:192$55' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:256$68' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:281$71' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:284$72' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:299$76' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$not$rtl/simple_spi_top.v:327$83' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.24. Executing AST frontend in derive mode using pre-parsed AST for module `$or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \B_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| |
| 11.25. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:133$26' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| |
| 11.26. Executing AST frontend in derive mode using pre-parsed AST for module `$or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.27. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:185$47' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:192$53' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.28. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 8'00010000 |
| Generating RTLIL representation for module `$paramod$90c97e5b9d799688a4270dd23bb7ed9d6b54debb$adff'. |
| |
| 11.29. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$345' using `$paramod$90c97e5b9d799688a4270dd23bb7ed9d6b54debb$adff'. |
| |
| 11.30. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 8'00000000 |
| Generating RTLIL representation for module `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| |
| 11.31. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$346' using `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| Mapping `simple_spi_top.$procdff$347' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 11.32. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 1'0 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 11.33. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$348' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `simple_spi_top.$procdff$349' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$350' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$351' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 11.34. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 12 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=12\CLK_POLARITY=1'1'. |
| |
| 11.35. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$352' using `$paramod$dff\WIDTH=12\CLK_POLARITY=1'1'. |
| |
| 11.36. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 3 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'. |
| |
| 11.37. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$353' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$354' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$355' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 11.38. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 2 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=2\CLK_POLARITY=1'1'. |
| |
| 11.39. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procdff$356' using `$paramod$dff\WIDTH=2\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$357' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$358' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procdff$359' using `$paramod$dff\WIDTH=2\CLK_POLARITY=1'1'. |
| Mapping `simple_spi_top.$procmux$142' using `$paramod$mux\WIDTH=8'. |
| Mapping `simple_spi_top.$procmux$146' using `$paramod$mux\WIDTH=8'. |
| Mapping `simple_spi_top.$procmux$153' using `$paramod$mux\WIDTH=8'. |
| Mapping `simple_spi_top.$procmux$155' using `$paramod$mux\WIDTH=8'. |
| |
| 11.40. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 8 |
| Parameter \S_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=8\S_WIDTH=3'. |
| |
| 11.41. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$159' using `$paramod$pmux\WIDTH=8\S_WIDTH=3'. |
| Mapping `simple_spi_top.$procmux$167' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$170' using `$paramod$mux\WIDTH=1'. |
| |
| 11.42. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 12 |
| Parameter \S_WIDTH = 11 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=12\S_WIDTH=11'. |
| |
| 11.43. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$173' using `$paramod$pmux\WIDTH=12\S_WIDTH=11'. |
| |
| 11.44. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 11.45. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$174_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$176_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$178_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$180_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$182_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$184_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$186_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$188_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$190_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$192_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$194_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 11.46. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=12'. |
| |
| 11.47. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$196' using `$paramod$mux\WIDTH=12'. |
| |
| 11.48. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=3'. |
| |
| 11.49. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$202' using `$paramod$mux\WIDTH=3'. |
| |
| 11.50. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 3 |
| Parameter \S_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=3\S_WIDTH=2'. |
| |
| 11.51. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$204' using `$paramod$pmux\WIDTH=3\S_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$205_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$209_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$215_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$217' using `$paramod$mux\WIDTH=3'. |
| Mapping `simple_spi_top.$procmux$222' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$224' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$226' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$239' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$244' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$246' using `$paramod$mux\WIDTH=1'. |
| |
| 11.52. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 1 |
| Parameter \S_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=3'. |
| |
| 11.53. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$248' using `$paramod$pmux\WIDTH=1\S_WIDTH=3'. |
| Mapping `simple_spi_top.$procmux$251' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$257' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$259' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$264' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$269' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$271' using `$paramod$mux\WIDTH=2'. |
| |
| 11.54. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 2 |
| Parameter \S_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=2\S_WIDTH=3'. |
| |
| 11.55. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$273' using `$paramod$pmux\WIDTH=2\S_WIDTH=3'. |
| Mapping `simple_spi_top.$procmux$276' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$283' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$288' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$294' using `$paramod$mux\WIDTH=8'. |
| |
| 11.56. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 8 |
| Parameter \S_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=8\S_WIDTH=2'. |
| |
| 11.57. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$296' using `$paramod$pmux\WIDTH=8\S_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$309' using `$paramod$mux\WIDTH=8'. |
| Mapping `simple_spi_top.$procmux$323' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$325' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$328' using `$paramod$mux\WIDTH=1'. |
| Mapping `simple_spi_top.$procmux$332' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$334' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$337' using `$paramod$mux\WIDTH=2'. |
| |
| 11.58. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 12 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=1'. |
| |
| 11.59. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$reduce_or$rtl/simple_spi_top.v:237$62' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=1'. |
| |
| 11.60. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.61. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$reduce_or$rtl/simple_spi_top.v:237$63' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.62. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| |
| 11.63. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$reduce_or$rtl/simple_spi_top.v:299$75' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$reduce_or$rtl/simple_spi_top.v:322$80' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.64. Executing AST frontend in derive mode using pre-parsed AST for module `$sub'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 12 |
| Parameter \B_WIDTH = 11 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=11\Y_WIDTH=12'. |
| |
| 11.65. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66' using `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=11\Y_WIDTH=12'. |
| |
| 11.66. Executing AST frontend in derive mode using pre-parsed AST for module `$sub'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.67. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74' using `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.68. Executing AST frontend in derive mode using pre-parsed AST for module `$sub'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.69. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81' using `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.70. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.71. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.72. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=2'. |
| |
| 11.73. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88.alu' using `$paramod$alu\WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92.alu' using `$paramod$alu\WIDTH=2'. |
| |
| 11.74. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.75. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:122$97.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:122$97.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:123$99.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:123$99.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:131$103.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$and$rtl/fifo4.v:131$103.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:122$95.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:122$95.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:131$102.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$eq$rtl/fifo4.v:131$102.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.76. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_bool'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| |
| 11.77. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$logic_not$rtl/fifo4.v:106$91.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$logic_not$rtl/fifo4.v:122$96.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[0][0]$380.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[0][0]$380.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[1][0]$386.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[1][0]$386.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[2][0]$392.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[2][0]$392.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[3][0]$398.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wren[3][0]$398.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[0][0]$378.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[0][0]$378.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[1][0]$384.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[1][0]$384.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[2][0]$390.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[2][0]$390.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[3][0]$396.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$memory$mem$\mem$360$wreq[3][0]$396.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:122$95.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:122$95.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 11.78. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.79. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:122$95.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:131$102.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:131$102.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:131$102.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[0][0]$378.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[0][0]$378.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[1][0]$384.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[1][0]$384.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[2][0]$390.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[2][0]$390.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[3][0]$396.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[3][0]$396.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:120$21.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:120$21.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:121$22.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:121$22.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$29.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$29.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$30.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$30.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$31.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:140$31.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:141$32.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:141$32.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:153$38.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:153$38.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:160$42.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:160$42.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:178$44.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:178$44.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$48.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$48.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$50.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:185$50.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$54.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$54.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$56.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:192$56.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:205$58.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:205$58.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$64.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$64.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$65.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:237$65.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:327$84.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$and$rtl/simple_spi_top.v:327$84.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:132$25.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:132$25.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:135$27.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:135$27.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:140$28.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:140$28.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:178$43.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$eq$rtl/simple_spi_top.v:178$43.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$logic_not$rtl/simple_spi_top.v:160$41.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| |
| 11.80. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| |
| 11.81. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:133$26.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:133$26.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:185$47.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:185$47.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:192$53.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$or$rtl/simple_spi_top.v:192$53.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.82. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 11.83. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$procmux$174_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$174_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$176_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$176_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$178_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$178_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$180_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$180_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$182_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$182_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$184_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$184_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$186_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$186_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$188_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$188_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$190_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$190_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$192_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$192_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$194_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$194_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$procmux$205_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$205_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$209_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$209_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$215_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$procmux$215_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.84. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 12 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.85. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.86. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 11 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=11\Y_WIDTH=12'. |
| |
| 11.87. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=11\Y_WIDTH=12'. |
| |
| 11.88. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=12'. |
| |
| 11.89. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu' using `$paramod$alu\WIDTH=12'. |
| |
| 11.90. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.91. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.92. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=3'. |
| |
| 11.93. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.alu' using `$paramod$alu\WIDTH=3'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81.alu' using `$paramod$alu\WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:132$25.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:132$25.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:135$27.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:135$27.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:140$28.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:140$28.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:178$43.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:178$43.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.94. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \B_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| |
| 11.95. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$434' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$435' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$436' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$437' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$438' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$439' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$440' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$441' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$442' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$443' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$444' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$reduce_or$<stdcells.v>:1214$432' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$ternary$<stdcells.v>:1214$433' using `$paramod$mux\WIDTH=8'. |
| |
| 11.96. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 12 |
| Parameter \B_WIDTH = 12 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.97. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$447' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$448' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$449' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$450' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$451' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$452' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$453' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$454' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$455' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$456' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$457' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=12\B_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.98. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 11 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| |
| 11.99. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=11\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$ternary$<stdcells.v>:1214$446' using `$paramod$mux\WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 11.100. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 11.101. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 11.102. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 11.103. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$180_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$182_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$184_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$184_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$188_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$190_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$192_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$194_CMP0.$not$<stdcells.v>:808$472' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 11.104. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.105. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$475' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$476' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$reduce_or$<stdcells.v>:1210$477' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$reduce_or$<stdcells.v>:1210$478' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$reduce_or$<stdcells.v>:1210$479' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$reduce_or$<stdcells.v>:1214$473' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$ternary$<stdcells.v>:1214$474' using `$paramod$mux\WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$205_CMP0.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$205_CMP0.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$205_CMP0.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$209_CMP0.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$209_CMP0.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$215_CMP0.$not$<stdcells.v>:808$431' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$215_CMP0.$reduce_or$<stdcells.v>:808$430' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$482' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$483' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$484' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$reduce_or$<stdcells.v>:1210$485' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$reduce_or$<stdcells.v>:1214$480' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$ternary$<stdcells.v>:1214$481' using `$paramod$mux\WIDTH=1'. |
| |
| 11.106. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.107. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$488' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$489' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$490' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$reduce_or$<stdcells.v>:1210$491' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$reduce_or$<stdcells.v>:1210$492' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$ternary$<stdcells.v>:1214$487' using `$paramod$mux\WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$495' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$496' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$497' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$498' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$499' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$500' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$501' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$502' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$503' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1210$504' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$reduce_or$<stdcells.v>:1214$493' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$ternary$<stdcells.v>:1214$494' using `$paramod$mux\WIDTH=8'. |
| |
| 11.108. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 12 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.109. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505' using `$paramod$not\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.110. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.111. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506' using `$paramod$not\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.112. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.113. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$sub$rtl/simple_spi_top.v:323$81.$not$<stdcells.v>:942$507' using `$paramod$not\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88.alu.V[0].adder' using `$fulladd'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:102$88.alu.V[1].adder' using `$fulladd'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92.alu.V[0].adder' using `$fulladd'. |
| Mapping `$paramod\fifo4\dw=8.$add$rtl/fifo4.v:112$92.alu.V[1].adder' using `$fulladd'. |
| |
| 11.114. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 11.115. Continuing TECHMAP pass. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:122$95.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:122$95.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:131$102.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$eq$rtl/fifo4.v:131$102.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `$paramod\fifo4\dw=8.$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[10].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[11].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[1].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[2].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[3].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[4].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[5].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[6].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[7].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[8].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:238$66.alu.V[9].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.alu.V[1].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:297$74.alu.V[2].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$sub$rtl/simple_spi_top.v:323$81.alu.V[1].adder' using `$fulladd'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$434.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$434.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$435.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$435.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$436.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$159.$and$<stdcells.v>:1203$436.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| |
| 11.116. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 12 |
| Parameter \Y_WIDTH = 12 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.117. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$447.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$447.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$448.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$448.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$449.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$449.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$450.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$450.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$451.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$451.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$452.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$452.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$453.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$453.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$454.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$454.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$455.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$455.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$456.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$456.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$457.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| Mapping `simple_spi_top.$techmap$procmux$173.$and$<stdcells.v>:1203$457.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=12\Y_WIDTH=12'. |
| |
| 11.118. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 11.119. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `simple_spi_top.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 11.120. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 11.121. Continuing TECHMAP pass. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$475.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$475.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$476.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$204.$and$<stdcells.v>:1203$476.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `simple_spi_top.$techmap$procmux$205_CMP0.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$205_CMP0.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$482.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$482.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$483.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$483.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$484.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$248.$and$<stdcells.v>:1203$484.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$488.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$488.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$489.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$489.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$490.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$273.$and$<stdcells.v>:1203$490.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$495.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$495.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$496.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `simple_spi_top.$techmap$procmux$296.$and$<stdcells.v>:1203$496.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| No more expansions possible. |
| |
| 12. Executing OPT pass (performing simple optimizations). |
| |
| 12.1. Optimizing in-memory representation of design. |
| |
| 12.2. Executing OPT_CONST pass (perform const folding). |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:102$88.alu.V[0].adder.gate1' (?1) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[0].adder.t1 = $procdff$344.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:102$88.alu.V[0].adder.gate3' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/fifo4.v:102$88.alu.V[0].adder.gate4' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[0].adder.Y = $add$rtl/fifo4.v:102$88.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:102$88.alu.V[1].adder.gate1' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/fifo4.v:102$88.alu.V[1].adder.gate2' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[1].adder.t2 = $procdff$344.Q [1]'. |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:112$92.alu.V[0].adder.gate1' (?1) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[0].adder.t1 = $procdff$339.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:112$92.alu.V[0].adder.gate3' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/fifo4.v:112$92.alu.V[0].adder.gate4' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[0].adder.Y = $add$rtl/fifo4.v:112$92.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/fifo4.v:112$92.alu.V[1].adder.gate1' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/fifo4.v:112$92.alu.V[1].adder.gate2' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[1].adder.t2 = $procdff$339.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.V[0].gate' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.Y [0] = $procmux$113.Y [0]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.V[1].gate' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$techmap$memory$mem$\mem$360$wreq[0][0]$378.$xor$<stdcells.v>:808$429.Y [1] = $procmux$113.Y [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.V[1].gate' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.Y [1] = $procmux$113.Y [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.V[0].gate' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.Y [0] = $procmux$113.Y [0]'. |
| Replacing $_OR_ cell `$add$rtl/fifo4.v:102$88.alu.V[0].adder.gate5' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[0].adder.X = $procdff$344.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/fifo4.v:102$88.alu.V[1].adder.gate5' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:102$88.alu.V[1].adder.X = $add$rtl/fifo4.v:102$88.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/fifo4.v:112$92.alu.V[0].adder.gate5' (?0) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[0].adder.X = $procdff$339.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/fifo4.v:112$92.alu.V[1].adder.gate5' (0?) in module `$paramod\fifo4\dw=8' with constant driver `$add$rtl/fifo4.v:112$92.alu.V[1].adder.X = $add$rtl/fifo4.v:112$92.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [0] = \dat_i [0]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [1] = \dat_i [1]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [2] = \dat_i [2]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [3] = \dat_i [3]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[4].gate' (?1) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [4] = 1'1'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[5].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [5] = \dat_i [5]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[6].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [6] = \dat_i [6]'. |
| Replacing $_OR_ cell `$or$rtl/simple_spi_top.v:133$26.V[7].gate' (?0) in module `\simple_spi_top' with constant driver `$or$rtl/simple_spi_top.v:133$26.Y [7] = \dat_i [7]'. |
| Replacing $_MUX_ cell `$procmux$269.V[1].gate' (00?) in module `\simple_spi_top' with constant driver `$procmux$269.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.gate3' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.t3 = $sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.gate3' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.t3 = $sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.gate3' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.t3 = $sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.t2'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.Y [0] = \adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$eq$rtl/simple_spi_top.v:132$25.$xor$<stdcells.v>:808$429.Y [1] = \adr_i [1]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.Y [0] = \adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.Y [1] = \adr_i [1]'. |
| Replacing $_AND_ cell `$techmap$procmux$159.$and$<stdcells.v>:1203$435.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$159.$and$<stdcells.v>:1203$435.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$159.$and$<stdcells.v>:1203$435.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$159.$and$<stdcells.v>:1203$435.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [0] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [1] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [2] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [3] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [4] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[5].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [5] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[6].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [6] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[7].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [7] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[8].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [8] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$447.V[9].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$447.Y [9] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [0] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [1] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [2] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [3] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [4] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[5].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [5] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[6].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [6] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[7].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [7] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[8].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [8] = $techmap$procmux$176_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$448.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$448.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [0] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [1] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [2] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [3] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [4] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[5].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [5] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[6].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [6] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[7].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [7] = $techmap$procmux$178_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$449.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$449.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [0] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [1] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [2] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [3] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [4] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[5].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [5] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[6].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [6] = $techmap$procmux$180_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$450.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$450.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [0] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [1] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [2] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [3] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [4] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[5].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [5] = $techmap$procmux$182_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$451.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$451.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [0] = $techmap$procmux$184_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [1] = $techmap$procmux$184_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [2] = $techmap$procmux$184_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$452.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$452.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [0] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [1] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [2] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [3] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[4].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [4] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$453.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$453.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [0] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [1] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [2] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[3].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [3] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$454.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$454.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [0] = $techmap$procmux$190_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [1] = $techmap$procmux$190_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$455.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$455.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [0] = $techmap$procmux$192_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[1].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$456.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$456.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[0].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[11].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[1].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$173.$and$<stdcells.v>:1203$457.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$and$<stdcells.v>:1203$457.Y [9] = 1'0'. |
| Replacing $_XOR_ cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $procdff$345.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $procdff$345.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $procdff$346.Q [1]'. |
| Replacing $_AND_ cell `$techmap$procmux$204.$and$<stdcells.v>:1203$476.V[0].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$204.$and$<stdcells.v>:1203$476.Y [0] = $techmap$procmux$215_CMP0.$not$<stdcells.v>:808$431.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$204.$and$<stdcells.v>:1203$476.V[1].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$204.$and$<stdcells.v>:1203$476.Y [1] = $techmap$procmux$215_CMP0.$not$<stdcells.v>:808$431.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$204.$and$<stdcells.v>:1203$476.V[2].gate' (1?) in module `\simple_spi_top' with constant driver `$techmap$procmux$204.$and$<stdcells.v>:1203$476.Y [2] = $techmap$procmux$215_CMP0.$not$<stdcells.v>:808$431.Y'. |
| Replacing $_XOR_ cell `$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.Y [1] = $procdff$356.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.V[0].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.Y [0] = $procdff$356.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.V[1].gate' (?0) in module `\simple_spi_top' with constant driver `$techmap$procmux$215_CMP0.$xor$<stdcells.v>:808$429.Y [1] = $procdff$356.Q [1]'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[0].gate' (1) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [0] = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[10].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [10] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[11].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [11] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[1].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [1] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[2].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [2] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[3].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [3] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[4].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [4] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[5].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [5] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[6].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [6] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[7].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [7] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[8].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [8] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.V[9].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:238$66.$not$<stdcells.v>:942$505.Y [9] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.V[0].gate' (1) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.Y [0] = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.V[1].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.Y [1] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.V[2].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:297$74.$not$<stdcells.v>:942$506.Y [2] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:323$81.$not$<stdcells.v>:942$507.V[0].gate' (1) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:323$81.$not$<stdcells.v>:942$507.Y [0] = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/simple_spi_top.v:323$81.$not$<stdcells.v>:942$507.V[1].gate' (0) in module `\simple_spi_top' with constant driver `$techmap$sub$rtl/simple_spi_top.v:323$81.$not$<stdcells.v>:942$507.Y [1] = 1'1'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.gate1' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.gate2' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.t2 = $procdff$352.Q [0]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[10].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[10].adder.t1 = $procdff$352.Q [10]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[11].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[11].adder.t1 = $procdff$352.Q [11]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[1].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[1].adder.t1 = $procdff$352.Q [1]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[2].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[2].adder.t1 = $procdff$352.Q [2]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[3].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[3].adder.t1 = $procdff$352.Q [3]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[4].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[4].adder.t1 = $procdff$352.Q [4]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[5].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[5].adder.t1 = $procdff$352.Q [5]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[6].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[6].adder.t1 = $procdff$352.Q [6]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[7].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[7].adder.t1 = $procdff$352.Q [7]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[8].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[8].adder.t1 = $procdff$352.Q [8]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[9].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[9].adder.t1 = $procdff$352.Q [9]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.gate1' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.gate2' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.t2 = $procdff$353.Q [0]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[1].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[1].adder.t1 = $procdff$353.Q [1]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[2].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[2].adder.t1 = $procdff$353.Q [2]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.gate1' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.gate2' (?0) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.t2 = $procdff$359.Q [0]'. |
| Replacing $_AND_ cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[1].adder.gate1' (?1) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:323$81.alu.V[1].adder.t1 = $procdff$359.Q [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$441.V[1].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$441.buffer [1] = $techmap$procmux$159.$and$<stdcells.v>:1203$434.Y [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$442.V[1].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$159.$reduce_or$<stdcells.v>:1210$442.buffer [1] = $techmap$procmux$159.$and$<stdcells.v>:1203$434.Y [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[1].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [1] = $techmap$procmux$174_CMP0.$not$<stdcells.v>:808$472.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$467.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[1].gate' (00) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$468.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[10].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [10] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[1].gate' (00) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[2].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[3].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[4].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[5].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[6].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[7].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[8].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.V[9].gate' (0?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$469.buffer [8]'. |
| Replacing $_OR_ cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.gate5' (0?) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:238$66.alu.V[0].adder.X = $procdff$352.Q [0]'. |
| Replacing $_OR_ cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.gate5' (0?) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:297$74.alu.V[0].adder.X = $procdff$353.Q [0]'. |
| Replacing $_OR_ cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.gate5' (0?) in module `\simple_spi_top' with constant driver `$sub$rtl/simple_spi_top.v:323$81.alu.V[0].adder.X = $procdff$359.Q [0]'. |
| Replacing $_MUX_ cell `$techmap$procmux$173.$ternary$<stdcells.v>:1214$446.V[11].gate' (00?) in module `\simple_spi_top' with constant driver `$techmap$procmux$173.$ternary$<stdcells.v>:1214$446.Y [11] = 1'0'. |
| |
| 12.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Cell `$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.V[0].gate' is identical to cell `$techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.V[0].gate'. |
| Redirecting output \Y: $techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.Y [0] = $techmap$memory$mem$\mem$360$wreq[1][0]$384.$xor$<stdcells.v>:808$429.Y [0] |
| Removing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.V[0].gate' from module `$paramod\fifo4\dw=8'. |
| Cell `$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.V[1].gate' is identical to cell `$techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.V[1].gate'. |
| Redirecting output \Y: $techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.Y [1] = $techmap$memory$mem$\mem$360$wreq[2][0]$390.$xor$<stdcells.v>:808$429.Y [1] |
| Removing $_XOR_ cell `$techmap$memory$mem$\mem$360$wreq[3][0]$396.$xor$<stdcells.v>:808$429.V[1].gate' from module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Cell `$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.V[1].gate' is identical to cell `$techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.V[1].gate'. |
| Redirecting output \Y: $techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.Y [1] = $techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.Y [1] |
| Removing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:140$28.$xor$<stdcells.v>:808$429.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.V[0].gate' is identical to cell `$techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.V[0].gate'. |
| Redirecting output \Y: $techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.Y [0] = $techmap$eq$rtl/simple_spi_top.v:135$27.$xor$<stdcells.v>:808$429.Y [0] |
| Removing $_XOR_ cell `$techmap$eq$rtl/simple_spi_top.v:178$43.$xor$<stdcells.v>:808$429.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[5].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[5].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[6].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[6].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[7].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[7].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[8].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$459.V[8].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[5].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[5].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[6].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[6].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[7].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$460.V[7].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[6].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$461.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$462.V[6].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$463.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$464.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$465.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$466.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[1].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [1] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[2].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [2] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[3].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [3] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[4].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [4] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[4].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[5].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [5] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[5].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[6].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [6] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[6].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[7].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [7] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[7].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[8].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [8] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[8].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[9].gate' is identical to cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.buffer [9] = $techmap$procmux$173.$reduce_or$<stdcells.v>:1210$458.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$173.$reduce_or$<stdcells.v>:1214$445.V[9].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [3] |
| Removing $_XOR_ cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.Y [3] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [3] |
| Removing $_XOR_ cell `$techmap$procmux$178_CMP0.$xor$<stdcells.v>:808$470.V[3].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' is identical to cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' is identical to cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [2] |
| Removing $_XOR_ cell `$techmap$procmux$182_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' is identical to cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' is identical to cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [2] |
| Removing $_XOR_ cell `$techmap$procmux$184_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' is identical to cell `$techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.Y [2] = $techmap$procmux$180_CMP0.$xor$<stdcells.v>:808$470.Y [2] |
| Removing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$470.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' is identical to cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.Y [1] = $techmap$procmux$174_CMP0.$xor$<stdcells.v>:808$470.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$190_CMP0.$xor$<stdcells.v>:808$470.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' is identical to cell `$techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.Y [0] = $techmap$procmux$176_CMP0.$xor$<stdcells.v>:808$470.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$470.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' is identical to cell `$techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] = $techmap$procmux$178_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.V[0].gate' is identical to cell `$techmap$procmux$205_CMP0.$xor$<stdcells.v>:808$429.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.Y [0] = $techmap$procmux$205_CMP0.$xor$<stdcells.v>:808$429.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$209_CMP0.$xor$<stdcells.v>:808$429.V[0].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$215_CMP0.$reduce_or$<stdcells.v>:808$430.V[1].gate' is identical to cell `$reduce_or$rtl/simple_spi_top.v:237$63.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$215_CMP0.$reduce_or$<stdcells.v>:808$430.buffer [1] = $reduce_or$rtl/simple_spi_top.v:237$63.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$215_CMP0.$reduce_or$<stdcells.v>:808$430.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.V[1].gate' is identical to cell `$techmap$procmux$248.$reduce_or$<stdcells.v>:1214$480.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.buffer [1] = $techmap$procmux$248.$reduce_or$<stdcells.v>:1214$480.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.V[2].gate' is identical to cell `$techmap$procmux$248.$reduce_or$<stdcells.v>:1214$480.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.buffer [2] = $techmap$procmux$248.$reduce_or$<stdcells.v>:1214$480.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$273.$reduce_or$<stdcells.v>:1214$486.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$296.$reduce_or$<stdcells.v>:1214$493.V[1].gate' is identical to cell `$techmap$procmux$204.$reduce_or$<stdcells.v>:1214$473.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$296.$reduce_or$<stdcells.v>:1214$493.buffer [1] = $techmap$procmux$204.$reduce_or$<stdcells.v>:1214$473.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$296.$reduce_or$<stdcells.v>:1214$493.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$182_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$182_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$182_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$184_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$184_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$184_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$180_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$180_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' is identical to cell `$techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] = $techmap$procmux$174_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$190_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' is identical to cell `$techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] = $techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.V[1].gate' from module `\simple_spi_top'. |
| Cell `$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' is identical to cell `$techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] = $techmap$procmux$176_CMP0.$reduce_or$<stdcells.v>:808$471.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$471.V[2].gate' from module `\simple_spi_top'. |
| Removed a total of 75 cells. |
| |
| 12.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 12.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 12.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 12.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 12.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| removing unused `$_AND_' cell `$add$rtl/fifo4.v:112$92.alu.V[1].adder.gate3'. |
| removing unused `$_AND_' cell `$add$rtl/fifo4.v:102$88.alu.V[1].adder.gate3'. |
| removed 398 unused temporary wires. |
| Finding unused cells or wires in module \simple_spi_top.. |
| removing unused `$_AND_' cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[11].adder.gate3'. |
| removing unused `$_OR_' cell `$sub$rtl/simple_spi_top.v:238$66.alu.V[11].adder.gate5'. |
| removing unused `$_AND_' cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[2].adder.gate3'. |
| removing unused `$_OR_' cell `$sub$rtl/simple_spi_top.v:297$74.alu.V[2].adder.gate5'. |
| removing unused `$_AND_' cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[1].adder.gate3'. |
| removing unused `$_OR_' cell `$sub$rtl/simple_spi_top.v:323$81.alu.V[1].adder.gate5'. |
| removed 1525 unused temporary wires. |
| |
| 12.9. Executing OPT_CONST pass (perform const folding). |
| |
| 12.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 12.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 12.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 12.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 12.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| Finding unused cells or wires in module \simple_spi_top.. |
| |
| 12.16. Executing OPT_CONST pass (perform const folding). |
| |
| 12.17. Optimizing in-memory representation of design. |
| |
| 12.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 13. Executing ABC pass (technology mapping using ABC). |
| |
| 13.1. Extracting gate logic of module `$paramod\fifo4\dw=8' to `/tmp/yosys-abc-qrUJ8F/input.v'.. |
| Extracted 110 gates and 162 wires to a logic network with 49 inputs and 47 outputs. |
| |
| 13.1.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-qrUJ8F/input.v; read_library /tmp/yosys-abc-qrUJ8F/stdcells.genlib; map; write_verilog /tmp/yosys-abc-qrUJ8F/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-qrUJ8F/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-qrUJ8F/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-qrUJ8F/stdcells.super". Time = 0.00 sec |
| |
| 13.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 25 |
| ABC RESULTS: INV cells: 10 |
| ABC RESULTS: MUX cells: 58 |
| ABC RESULTS: OR cells: 9 |
| ABC RESULTS: XOR cells: 6 |
| ABC RESULTS: internal signals: 66 |
| ABC RESULTS: input signals: 49 |
| ABC RESULTS: output signals: 47 |
| |
| 13.1.3. Removing temp directory `/tmp/yosys-abc-qrUJ8F': |
| Removing `/tmp/yosys-abc-qrUJ8F/input.v'. |
| Removing `/tmp/yosys-abc-qrUJ8F/output.v'. |
| Removing `/tmp/yosys-abc-qrUJ8F/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-qrUJ8F/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-qrUJ8F/stdcells.super'. |
| Removing `/tmp/yosys-abc-qrUJ8F'. |
| |
| 13.2. Extracting gate logic of module `\simple_spi_top' to `/tmp/yosys-abc-BbRKpJ/input.v'.. |
| Extracted 379 gates and 463 wires to a logic network with 82 inputs and 61 outputs. |
| |
| 13.2.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-BbRKpJ/input.v; read_library /tmp/yosys-abc-BbRKpJ/stdcells.genlib; map; write_verilog /tmp/yosys-abc-BbRKpJ/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-BbRKpJ/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-BbRKpJ/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-BbRKpJ/stdcells.super". Time = 0.00 sec |
| |
| 13.2.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 115 |
| ABC RESULTS: INV cells: 47 |
| ABC RESULTS: MUX cells: 83 |
| ABC RESULTS: OR cells: 94 |
| ABC RESULTS: XOR cells: 16 |
| ABC RESULTS: internal signals: 320 |
| ABC RESULTS: input signals: 82 |
| ABC RESULTS: output signals: 61 |
| |
| 13.2.3. Removing temp directory `/tmp/yosys-abc-BbRKpJ': |
| Removing `/tmp/yosys-abc-BbRKpJ/input.v'. |
| Removing `/tmp/yosys-abc-BbRKpJ/output.v'. |
| Removing `/tmp/yosys-abc-BbRKpJ/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-BbRKpJ/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-BbRKpJ/stdcells.super'. |
| Removing `/tmp/yosys-abc-BbRKpJ'. |
| |
| 14. Executing OPT pass (performing simple optimizations). |
| |
| 14.1. Optimizing in-memory representation of design. |
| |
| 14.2. Executing OPT_CONST pass (perform const folding). |
| |
| 14.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 14.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module $paramod\fifo4\dw=8.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \simple_spi_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 14.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module $paramod\fifo4\dw=8. |
| Optimizing cells in module \simple_spi_top. |
| Performed a total of 0 changes. |
| |
| 14.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `$paramod\fifo4\dw=8'. |
| Finding identical cells in module `\simple_spi_top'. |
| Removed a total of 0 cells. |
| |
| 14.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 14.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module $paramod\fifo4\dw=8.. |
| removing unused non-port wire \rp_p1. |
| removing unused non-port wire \wp_p1. |
| removed 131 unused temporary wires. |
| Finding unused cells or wires in module \simple_spi_top.. |
| removing unused non-port wire \ena. |
| removing unused non-port wire \tirq. |
| removing unused non-port wire \wb_acc. |
| removing unused non-port wire \wb_wr. |
| removing unused non-port wire \wfov. |
| removing unused non-port wire \wr_spsr. |
| removed 300 unused temporary wires. |
| |
| 14.9. Executing OPT_CONST pass (perform const folding). |
| |
| 14.10. Optimizing in-memory representation of design. |
| |
| 14.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 15. Executing Verilog backend. |
| Full command line: write_verilog -noattr output/synth.v |
| Dumping module `$paramod\fifo4\dw=8'. |
| renaming `$0\gb[0:0]' to `_000_'. |
| renaming `$0\rp[1:0]' to `_001_'. |
| renaming `$0\wp[1:0]' to `_002_'. |
| renaming `$abc$508$g000' to `_068_'. |
| renaming `$abc$508$g001' to `_069_'. |
| renaming `$abc$508$g002' to `_070_'. |
| renaming `$abc$508$g003' to `_071_'. |
| renaming `$abc$508$g004' to `_072_'. |
| renaming `$abc$508$g005' to `_073_'. |
| renaming `$abc$508$g006' to `_074_'. |
| renaming `$abc$508$g007' to `_075_'. |
| renaming `$abc$508$g008' to `_076_'. |
| renaming `$abc$508$g009' to `_077_'. |
| renaming `$abc$508$g010' to `_078_'. |
| renaming `$abc$508$g011' to `_079_'. |
| renaming `$abc$508$g012' to `_080_'. |
| renaming `$abc$508$g013' to `_081_'. |
| renaming `$abc$508$g014' to `_082_'. |
| renaming `$abc$508$g015' to `_083_'. |
| renaming `$abc$508$g016' to `_084_'. |
| renaming `$abc$508$g017' to `_085_'. |
| renaming `$abc$508$g018' to `_086_'. |
| renaming `$abc$508$g019' to `_087_'. |
| renaming `$abc$508$g020' to `_088_'. |
| renaming `$abc$508$g021' to `_089_'. |
| renaming `$abc$508$g022' to `_090_'. |
| renaming `$abc$508$g023' to `_091_'. |
| renaming `$abc$508$g024' to `_092_'. |
| renaming `$abc$508$g025' to `_093_'. |
| renaming `$abc$508$g026' to `_094_'. |
| renaming `$abc$508$g027' to `_095_'. |
| renaming `$abc$508$g028' to `_096_'. |
| renaming `$abc$508$g029' to `_097_'. |
| renaming `$abc$508$g030' to `_098_'. |
| renaming `$abc$508$g031' to `_099_'. |
| renaming `$abc$508$g032' to `_100_'. |
| renaming `$abc$508$g033' to `_101_'. |
| renaming `$abc$508$g034' to `_102_'. |
| renaming `$abc$508$g035' to `_103_'. |
| renaming `$abc$508$g036' to `_104_'. |
| renaming `$abc$508$g037' to `_105_'. |
| renaming `$abc$508$g038' to `_106_'. |
| renaming `$abc$508$g039' to `_107_'. |
| renaming `$abc$508$g040' to `_108_'. |
| renaming `$abc$508$g041' to `_109_'. |
| renaming `$abc$508$g042' to `_110_'. |
| renaming `$abc$508$g043' to `_111_'. |
| renaming `$abc$508$g044' to `_112_'. |
| renaming `$abc$508$g045' to `_113_'. |
| renaming `$abc$508$g046' to `_114_'. |
| renaming `$abc$508$g047' to `_115_'. |
| renaming `$abc$508$g048' to `_116_'. |
| renaming `$abc$508$g049' to `_117_'. |
| renaming `$abc$508$g050' to `_118_'. |
| renaming `$abc$508$g051' to `_119_'. |
| renaming `$abc$508$g052' to `_120_'. |
| renaming `$abc$508$g053' to `_121_'. |
| renaming `$abc$508$g054' to `_122_'. |
| renaming `$abc$508$g055' to `_123_'. |
| renaming `$abc$508$g056' to `_124_'. |
| renaming `$abc$508$g057' to `_125_'. |
| renaming `$abc$508$g058' to `_126_'. |
| renaming `$abc$508$g059' to `_127_'. |
| renaming `$abc$508$g060' to `_128_'. |
| renaming `$abc$508$g061' to `_129_'. |
| renaming `$abc$508$g062' to `_130_'. |
| renaming `$abc$508$g063' to `_131_'. |
| renaming `$abc$508$g064' to `_132_'. |
| renaming `$abc$508$g065' to `_133_'. |
| renaming `$abc$508$g066' to `_134_'. |
| renaming `$abc$508$g067' to `_135_'. |
| renaming `$abc$508$g068' to `_136_'. |
| renaming `$abc$508$g069' to `_137_'. |
| renaming `$abc$508$g070' to `_138_'. |
| renaming `$abc$508$g071' to `_139_'. |
| renaming `$abc$508$g072' to `_140_'. |
| renaming `$abc$508$g073' to `_141_'. |
| renaming `$abc$508$g074' to `_142_'. |
| renaming `$abc$508$g075' to `_143_'. |
| renaming `$abc$508$g076' to `_144_'. |
| renaming `$abc$508$g077' to `_145_'. |
| renaming `$abc$508$g078' to `_146_'. |
| renaming `$abc$508$g079' to `_147_'. |
| renaming `$abc$508$g080' to `_148_'. |
| renaming `$abc$508$g081' to `_149_'. |
| renaming `$abc$508$g082' to `_150_'. |
| renaming `$abc$508$g083' to `_151_'. |
| renaming `$abc$508$g084' to `_152_'. |
| renaming `$abc$508$g085' to `_153_'. |
| renaming `$abc$508$g086' to `_154_'. |
| renaming `$abc$508$g087' to `_155_'. |
| renaming `$abc$508$g088' to `_156_'. |
| renaming `$abc$508$g089' to `_157_'. |
| renaming `$abc$508$g090' to `_158_'. |
| renaming `$abc$508$g091' to `_159_'. |
| renaming `$abc$508$g092' to `_160_'. |
| renaming `$abc$508$g093' to `_161_'. |
| renaming `$abc$508$g094' to `_162_'. |
| renaming `$abc$508$g095' to `_163_'. |
| renaming `$abc$508$g096' to `_164_'. |
| renaming `$abc$508$g097' to `_165_'. |
| renaming `$abc$508$g098' to `_166_'. |
| renaming `$abc$508$g099' to `_167_'. |
| renaming `$abc$508$g100' to `_168_'. |
| renaming `$abc$508$g101' to `_169_'. |
| renaming `$abc$508$g102' to `_170_'. |
| renaming `$abc$508$g103' to `_171_'. |
| renaming `$abc$508$g104' to `_172_'. |
| renaming `$abc$508$g105' to `_173_'. |
| renaming `$abc$508$g106' to `_174_'. |
| renaming `$abc$508$g107' to `_175_'. |
| renaming `$abc$508$n100_1' to `_003_'. |
| renaming `$abc$508$n101_1' to `_004_'. |
| renaming `$abc$508$n104_1' to `_005_'. |
| renaming `$abc$508$n105_1' to `_006_'. |
| renaming `$abc$508$n107_1' to `_007_'. |
| renaming `$abc$508$n108_1' to `_008_'. |
| renaming `$abc$508$n110_1' to `_009_'. |
| renaming `$abc$508$n111_1' to `_010_'. |
| renaming `$abc$508$n113_1' to `_011_'. |
| renaming `$abc$508$n114_1' to `_012_'. |
| renaming `$abc$508$n116_1' to `_013_'. |
| renaming `$abc$508$n117_1' to `_014_'. |
| renaming `$abc$508$n119_1' to `_015_'. |
| renaming `$abc$508$n120_1' to `_016_'. |
| renaming `$abc$508$n122_1' to `_017_'. |
| renaming `$abc$508$n123_1' to `_018_'. |
| renaming `$abc$508$n125' to `_019_'. |
| renaming `$abc$508$n126' to `_020_'. |
| renaming `$abc$508$n128' to `_021_'. |
| renaming `$abc$508$n129_1' to `_022_'. |
| renaming `$abc$508$n130_1' to `_023_'. |
| renaming `$abc$508$n131' to `_024_'. |
| renaming `$abc$508$n132' to `_025_'. |
| renaming `$abc$508$n134_1' to `_026_'. |
| renaming `$abc$508$n136_1' to `_027_'. |
| renaming `$abc$508$n138_1' to `_028_'. |
| renaming `$abc$508$n140_1' to `_029_'. |
| renaming `$abc$508$n142' to `_030_'. |
| renaming `$abc$508$n144' to `_031_'. |
| renaming `$abc$508$n146' to `_032_'. |
| renaming `$abc$508$n148_1' to `_033_'. |
| renaming `$abc$508$n149_1' to `_034_'. |
| renaming `$abc$508$n158' to `_035_'. |
| renaming `$abc$508$n159' to `_036_'. |
| renaming `$abc$508$n160' to `_037_'. |
| renaming `$abc$508$n169' to `_038_'. |
| renaming `$abc$508$n178' to `_039_'. |
| renaming `$abc$508$n179' to `_040_'. |
| renaming `$abc$508$n181' to `_041_'. |
| renaming `$abc$508$n182' to `_042_'. |
| renaming `$abc$508$n183' to `_043_'. |
| renaming `$abc$508$n185' to `_044_'. |
| renaming `$abc$508$n186' to `_045_'. |
| renaming `$abc$508$n187' to `_046_'. |
| renaming `$abc$508$n188' to `_047_'. |
| renaming `$abc$508$n189' to `_048_'. |
| renaming `$abc$508$n190' to `_049_'. |
| renaming `$abc$508$n191' to `_050_'. |
| renaming `$abc$508$n192' to `_051_'. |
| renaming `$abc$508$n193' to `_052_'. |
| renaming `$abc$508$n194' to `_053_'. |
| renaming `$abc$508$n195' to `_054_'. |
| renaming `$abc$508$n196' to `_055_'. |
| renaming `$abc$508$n197' to `_056_'. |
| renaming `$abc$508$n198' to `_057_'. |
| renaming `$abc$508$n200' to `_058_'. |
| renaming `$abc$508$n202' to `_059_'. |
| renaming `$abc$508$n96' to `_060_'. |
| renaming `$abc$508$n97_1' to `_061_'. |
| renaming `$abc$508$n98' to `_062_'. |
| renaming `$abc$508$n99_1' to `_063_'. |
| renaming `$memory$mem$\mem$360$wrmux[0][0]$382.Y' to `_064_'. |
| renaming `$memory$mem$\mem$360$wrmux[1][0]$388.Y' to `_065_'. |
| renaming `$memory$mem$\mem$360$wrmux[2][0]$394.Y' to `_066_'. |
| renaming `$memory$mem$\mem$360$wrmux[3][0]$400.Y' to `_067_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[0].ff' to `_176_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[1].ff' to `_177_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[2].ff' to `_178_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[3].ff' to `_179_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[4].ff' to `_180_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[5].ff' to `_181_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[6].ff' to `_182_'. |
| renaming `$memory$mem$\mem$360[0]$361.V[7].ff' to `_183_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[0].ff' to `_184_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[1].ff' to `_185_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[2].ff' to `_186_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[3].ff' to `_187_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[4].ff' to `_188_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[5].ff' to `_189_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[6].ff' to `_190_'. |
| renaming `$memory$mem$\mem$360[1]$363.V[7].ff' to `_191_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[0].ff' to `_192_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[1].ff' to `_193_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[2].ff' to `_194_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[3].ff' to `_195_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[4].ff' to `_196_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[5].ff' to `_197_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[6].ff' to `_198_'. |
| renaming `$memory$mem$\mem$360[2]$365.V[7].ff' to `_199_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[0].ff' to `_200_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[1].ff' to `_201_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[2].ff' to `_202_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[3].ff' to `_203_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[4].ff' to `_204_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[5].ff' to `_205_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[6].ff' to `_206_'. |
| renaming `$memory$mem$\mem$360[3]$367.V[7].ff' to `_207_'. |
| renaming `$procdff$339.V[0].P.PN.PN0.ff' to `_208_'. |
| renaming `$procdff$339.V[1].P.PN.PN0.ff' to `_209_'. |
| renaming `$procdff$343.V[0].ff' to `_210_'. |
| renaming `$procdff$344.V[0].P.PN.PN0.ff' to `_211_'. |
| renaming `$procdff$344.V[1].P.PN.PN0.ff' to `_212_'. |
| Dumping module `\simple_spi_top'. |
| renaming `$0\ack_o[0:0]' to `_000_'. |
| renaming `$0\bcnt[2:0]' to `_001_'. |
| renaming `$0\clkcnt[11:0]' to `_002_'. |
| renaming `$0\dat_o[7:0]' to `_003_'. |
| renaming `$0\inta_o[0:0]' to `_004_'. |
| renaming `$0\rfwe[0:0]' to `_005_'. |
| renaming `$0\sck_o[0:0]' to `_006_'. |
| renaming `$0\spcr[7:0]' to `_007_'. |
| renaming `$0\sper[7:0]' to `_008_'. |
| renaming `$0\spif[0:0]' to `_009_'. |
| renaming `$0\state[1:0]' to `_010_'. |
| renaming `$0\tcnt[1:0]' to `_011_'. |
| renaming `$0\treg[7:0]' to `_012_'. |
| renaming `$0\wcol[0:0]' to `_013_'. |
| renaming `$0\wfre[0:0]' to `_014_'. |
| renaming `$abc$509$g000' to `_310_'. |
| renaming `$abc$509$g001' to `_311_'. |
| renaming `$abc$509$g002' to `_312_'. |
| renaming `$abc$509$g003' to `_313_'. |
| renaming `$abc$509$g004' to `_314_'. |
| renaming `$abc$509$g005' to `_315_'. |
| renaming `$abc$509$g006' to `_316_'. |
| renaming `$abc$509$g007' to `_317_'. |
| renaming `$abc$509$g008' to `_318_'. |
| renaming `$abc$509$g009' to `_319_'. |
| renaming `$abc$509$g010' to `_320_'. |
| renaming `$abc$509$g011' to `_321_'. |
| renaming `$abc$509$g012' to `_322_'. |
| renaming `$abc$509$g013' to `_323_'. |
| renaming `$abc$509$g014' to `_324_'. |
| renaming `$abc$509$g015' to `_325_'. |
| renaming `$abc$509$g016' to `_326_'. |
| renaming `$abc$509$g017' to `_327_'. |
| renaming `$abc$509$g018' to `_328_'. |
| renaming `$abc$509$g019' to `_329_'. |
| renaming `$abc$509$g020' to `_330_'. |
| renaming `$abc$509$g021' to `_331_'. |
| renaming `$abc$509$g022' to `_332_'. |
| renaming `$abc$509$g023' to `_333_'. |
| renaming `$abc$509$g024' to `_334_'. |
| renaming `$abc$509$g025' to `_335_'. |
| renaming `$abc$509$g026' to `_336_'. |
| renaming `$abc$509$g027' to `_337_'. |
| renaming `$abc$509$g028' to `_338_'. |
| renaming `$abc$509$g029' to `_339_'. |
| renaming `$abc$509$g030' to `_340_'. |
| renaming `$abc$509$g031' to `_341_'. |
| renaming `$abc$509$g032' to `_342_'. |
| renaming `$abc$509$g033' to `_343_'. |
| renaming `$abc$509$g034' to `_344_'. |
| renaming `$abc$509$g035' to `_345_'. |
| renaming `$abc$509$g036' to `_346_'. |
| renaming `$abc$509$g037' to `_347_'. |
| renaming `$abc$509$g038' to `_348_'. |
| renaming `$abc$509$g039' to `_349_'. |
| renaming `$abc$509$g040' to `_350_'. |
| renaming `$abc$509$g041' to `_351_'. |
| renaming `$abc$509$g042' to `_352_'. |
| renaming `$abc$509$g043' to `_353_'. |
| renaming `$abc$509$g044' to `_354_'. |
| renaming `$abc$509$g045' to `_355_'. |
| renaming `$abc$509$g046' to `_356_'. |
| renaming `$abc$509$g047' to `_357_'. |
| renaming `$abc$509$g048' to `_358_'. |
| renaming `$abc$509$g049' to `_359_'. |
| renaming `$abc$509$g050' to `_360_'. |
| renaming `$abc$509$g051' to `_361_'. |
| renaming `$abc$509$g052' to `_362_'. |
| renaming `$abc$509$g053' to `_363_'. |
| renaming `$abc$509$g054' to `_364_'. |
| renaming `$abc$509$g055' to `_365_'. |
| renaming `$abc$509$g056' to `_366_'. |
| renaming `$abc$509$g057' to `_367_'. |
| renaming `$abc$509$g058' to `_368_'. |
| renaming `$abc$509$g059' to `_369_'. |
| renaming `$abc$509$g060' to `_370_'. |
| renaming `$abc$509$g061' to `_371_'. |
| renaming `$abc$509$g062' to `_372_'. |
| renaming `$abc$509$g063' to `_373_'. |
| renaming `$abc$509$g064' to `_374_'. |
| renaming `$abc$509$g065' to `_375_'. |
| renaming `$abc$509$g066' to `_376_'. |
| renaming `$abc$509$g067' to `_377_'. |
| renaming `$abc$509$g068' to `_378_'. |
| renaming `$abc$509$g069' to `_379_'. |
| renaming `$abc$509$g070' to `_380_'. |
| renaming `$abc$509$g071' to `_381_'. |
| renaming `$abc$509$g072' to `_382_'. |
| renaming `$abc$509$g073' to `_383_'. |
| renaming `$abc$509$g074' to `_384_'. |
| renaming `$abc$509$g075' to `_385_'. |
| renaming `$abc$509$g076' to `_386_'. |
| renaming `$abc$509$g077' to `_387_'. |
| renaming `$abc$509$g078' to `_388_'. |
| renaming `$abc$509$g079' to `_389_'. |
| renaming `$abc$509$g080' to `_390_'. |
| renaming `$abc$509$g081' to `_391_'. |
| renaming `$abc$509$g082' to `_392_'. |
| renaming `$abc$509$g083' to `_393_'. |
| renaming `$abc$509$g084' to `_394_'. |
| renaming `$abc$509$g085' to `_395_'. |
| renaming `$abc$509$g086' to `_396_'. |
| renaming `$abc$509$g087' to `_397_'. |
| renaming `$abc$509$g088' to `_398_'. |
| renaming `$abc$509$g089' to `_399_'. |
| renaming `$abc$509$g090' to `_400_'. |
| renaming `$abc$509$g091' to `_401_'. |
| renaming `$abc$509$g092' to `_402_'. |
| renaming `$abc$509$g093' to `_403_'. |
| renaming `$abc$509$g094' to `_404_'. |
| renaming `$abc$509$g095' to `_405_'. |
| renaming `$abc$509$g096' to `_406_'. |
| renaming `$abc$509$g097' to `_407_'. |
| renaming `$abc$509$g098' to `_408_'. |
| renaming `$abc$509$g099' to `_409_'. |
| renaming `$abc$509$g100' to `_410_'. |
| renaming `$abc$509$g101' to `_411_'. |
| renaming `$abc$509$g102' to `_412_'. |
| renaming `$abc$509$g103' to `_413_'. |
| renaming `$abc$509$g104' to `_414_'. |
| renaming `$abc$509$g105' to `_415_'. |
| renaming `$abc$509$g106' to `_416_'. |
| renaming `$abc$509$g107' to `_417_'. |
| renaming `$abc$509$g108' to `_418_'. |
| renaming `$abc$509$g109' to `_419_'. |
| renaming `$abc$509$g110' to `_420_'. |
| renaming `$abc$509$g111' to `_421_'. |
| renaming `$abc$509$g112' to `_422_'. |
| renaming `$abc$509$g113' to `_423_'. |
| renaming `$abc$509$g114' to `_424_'. |
| renaming `$abc$509$g115' to `_425_'. |
| renaming `$abc$509$g116' to `_426_'. |
| renaming `$abc$509$g117' to `_427_'. |
| renaming `$abc$509$g118' to `_428_'. |
| renaming `$abc$509$g119' to `_429_'. |
| renaming `$abc$509$g120' to `_430_'. |
| renaming `$abc$509$g121' to `_431_'. |
| renaming `$abc$509$g122' to `_432_'. |
| renaming `$abc$509$g123' to `_433_'. |
| renaming `$abc$509$g124' to `_434_'. |
| renaming `$abc$509$g125' to `_435_'. |
| renaming `$abc$509$g126' to `_436_'. |
| renaming `$abc$509$g127' to `_437_'. |
| renaming `$abc$509$g128' to `_438_'. |
| renaming `$abc$509$g129' to `_439_'. |
| renaming `$abc$509$g130' to `_440_'. |
| renaming `$abc$509$g131' to `_441_'. |
| renaming `$abc$509$g132' to `_442_'. |
| renaming `$abc$509$g133' to `_443_'. |
| renaming `$abc$509$g134' to `_444_'. |
| renaming `$abc$509$g135' to `_445_'. |
| renaming `$abc$509$g136' to `_446_'. |
| renaming `$abc$509$g137' to `_447_'. |
| renaming `$abc$509$g138' to `_448_'. |
| renaming `$abc$509$g139' to `_449_'. |
| renaming `$abc$509$g140' to `_450_'. |
| renaming `$abc$509$g141' to `_451_'. |
| renaming `$abc$509$g142' to `_452_'. |
| renaming `$abc$509$g143' to `_453_'. |
| renaming `$abc$509$g144' to `_454_'. |
| renaming `$abc$509$g145' to `_455_'. |
| renaming `$abc$509$g146' to `_456_'. |
| renaming `$abc$509$g147' to `_457_'. |
| renaming `$abc$509$g148' to `_458_'. |
| renaming `$abc$509$g149' to `_459_'. |
| renaming `$abc$509$g150' to `_460_'. |
| renaming `$abc$509$g151' to `_461_'. |
| renaming `$abc$509$g152' to `_462_'. |
| renaming `$abc$509$g153' to `_463_'. |
| renaming `$abc$509$g154' to `_464_'. |
| renaming `$abc$509$g155' to `_465_'. |
| renaming `$abc$509$g156' to `_466_'. |
| renaming `$abc$509$g157' to `_467_'. |
| renaming `$abc$509$g158' to `_468_'. |
| renaming `$abc$509$g159' to `_469_'. |
| renaming `$abc$509$g160' to `_470_'. |
| renaming `$abc$509$g161' to `_471_'. |
| renaming `$abc$509$g162' to `_472_'. |
| renaming `$abc$509$g163' to `_473_'. |
| renaming `$abc$509$g164' to `_474_'. |
| renaming `$abc$509$g165' to `_475_'. |
| renaming `$abc$509$g166' to `_476_'. |
| renaming `$abc$509$g167' to `_477_'. |
| renaming `$abc$509$g168' to `_478_'. |
| renaming `$abc$509$g169' to `_479_'. |
| renaming `$abc$509$g170' to `_480_'. |
| renaming `$abc$509$g171' to `_481_'. |
| renaming `$abc$509$g172' to `_482_'. |
| renaming `$abc$509$g173' to `_483_'. |
| renaming `$abc$509$g174' to `_484_'. |
| renaming `$abc$509$g175' to `_485_'. |
| renaming `$abc$509$g176' to `_486_'. |
| renaming `$abc$509$g177' to `_487_'. |
| renaming `$abc$509$g178' to `_488_'. |
| renaming `$abc$509$g179' to `_489_'. |
| renaming `$abc$509$g180' to `_490_'. |
| renaming `$abc$509$g181' to `_491_'. |
| renaming `$abc$509$g182' to `_492_'. |
| renaming `$abc$509$g183' to `_493_'. |
| renaming `$abc$509$g184' to `_494_'. |
| renaming `$abc$509$g185' to `_495_'. |
| renaming `$abc$509$g186' to `_496_'. |
| renaming `$abc$509$g187' to `_497_'. |
| renaming `$abc$509$g188' to `_498_'. |
| renaming `$abc$509$g189' to `_499_'. |
| renaming `$abc$509$g190' to `_500_'. |
| renaming `$abc$509$g191' to `_501_'. |
| renaming `$abc$509$g192' to `_502_'. |
| renaming `$abc$509$g193' to `_503_'. |
| renaming `$abc$509$g194' to `_504_'. |
| renaming `$abc$509$g195' to `_505_'. |
| renaming `$abc$509$g196' to `_506_'. |
| renaming `$abc$509$g197' to `_507_'. |
| renaming `$abc$509$g198' to `_508_'. |
| renaming `$abc$509$g199' to `_509_'. |
| renaming `$abc$509$g200' to `_510_'. |
| renaming `$abc$509$g201' to `_511_'. |
| renaming `$abc$509$g202' to `_512_'. |
| renaming `$abc$509$g203' to `_513_'. |
| renaming `$abc$509$g204' to `_514_'. |
| renaming `$abc$509$g205' to `_515_'. |
| renaming `$abc$509$g206' to `_516_'. |
| renaming `$abc$509$g207' to `_517_'. |
| renaming `$abc$509$g208' to `_518_'. |
| renaming `$abc$509$g209' to `_519_'. |
| renaming `$abc$509$g210' to `_520_'. |
| renaming `$abc$509$g211' to `_521_'. |
| renaming `$abc$509$g212' to `_522_'. |
| renaming `$abc$509$g213' to `_523_'. |
| renaming `$abc$509$g214' to `_524_'. |
| renaming `$abc$509$g215' to `_525_'. |
| renaming `$abc$509$g216' to `_526_'. |
| renaming `$abc$509$g217' to `_527_'. |
| renaming `$abc$509$g218' to `_528_'. |
| renaming `$abc$509$g219' to `_529_'. |
| renaming `$abc$509$g220' to `_530_'. |
| renaming `$abc$509$g221' to `_531_'. |
| renaming `$abc$509$g222' to `_532_'. |
| renaming `$abc$509$g223' to `_533_'. |
| renaming `$abc$509$g224' to `_534_'. |
| renaming `$abc$509$g225' to `_535_'. |
| renaming `$abc$509$g226' to `_536_'. |
| renaming `$abc$509$g227' to `_537_'. |
| renaming `$abc$509$g228' to `_538_'. |
| renaming `$abc$509$g229' to `_539_'. |
| renaming `$abc$509$g230' to `_540_'. |
| renaming `$abc$509$g231' to `_541_'. |
| renaming `$abc$509$g232' to `_542_'. |
| renaming `$abc$509$g233' to `_543_'. |
| renaming `$abc$509$g234' to `_544_'. |
| renaming `$abc$509$g235' to `_545_'. |
| renaming `$abc$509$g236' to `_546_'. |
| renaming `$abc$509$g237' to `_547_'. |
| renaming `$abc$509$g238' to `_548_'. |
| renaming `$abc$509$g239' to `_549_'. |
| renaming `$abc$509$g240' to `_550_'. |
| renaming `$abc$509$g241' to `_551_'. |
| renaming `$abc$509$g242' to `_552_'. |
| renaming `$abc$509$g243' to `_553_'. |
| renaming `$abc$509$g244' to `_554_'. |
| renaming `$abc$509$g245' to `_555_'. |
| renaming `$abc$509$g246' to `_556_'. |
| renaming `$abc$509$g247' to `_557_'. |
| renaming `$abc$509$g248' to `_558_'. |
| renaming `$abc$509$g249' to `_559_'. |
| renaming `$abc$509$g250' to `_560_'. |
| renaming `$abc$509$g251' to `_561_'. |
| renaming `$abc$509$g252' to `_562_'. |
| renaming `$abc$509$g253' to `_563_'. |
| renaming `$abc$509$g254' to `_564_'. |
| renaming `$abc$509$g255' to `_565_'. |
| renaming `$abc$509$g256' to `_566_'. |
| renaming `$abc$509$g257' to `_567_'. |
| renaming `$abc$509$g258' to `_568_'. |
| renaming `$abc$509$g259' to `_569_'. |
| renaming `$abc$509$g260' to `_570_'. |
| renaming `$abc$509$g261' to `_571_'. |
| renaming `$abc$509$g262' to `_572_'. |
| renaming `$abc$509$g263' to `_573_'. |
| renaming `$abc$509$g264' to `_574_'. |
| renaming `$abc$509$g265' to `_575_'. |
| renaming `$abc$509$g266' to `_576_'. |
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| renaming `$abc$509$g269' to `_579_'. |
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| renaming `$abc$509$g271' to `_581_'. |
| renaming `$abc$509$g272' to `_582_'. |
| renaming `$abc$509$g273' to `_583_'. |
| renaming `$abc$509$g274' to `_584_'. |
| renaming `$abc$509$g275' to `_585_'. |
| renaming `$abc$509$g276' to `_586_'. |
| renaming `$abc$509$g277' to `_587_'. |
| renaming `$abc$509$g278' to `_588_'. |
| renaming `$abc$509$g279' to `_589_'. |
| renaming `$abc$509$g280' to `_590_'. |
| renaming `$abc$509$g281' to `_591_'. |
| renaming `$abc$509$g282' to `_592_'. |
| renaming `$abc$509$g283' to `_593_'. |
| renaming `$abc$509$g284' to `_594_'. |
| renaming `$abc$509$g285' to `_595_'. |
| renaming `$abc$509$g286' to `_596_'. |
| renaming `$abc$509$g287' to `_597_'. |
| renaming `$abc$509$g288' to `_598_'. |
| renaming `$abc$509$g289' to `_599_'. |
| renaming `$abc$509$g290' to `_600_'. |
| renaming `$abc$509$g291' to `_601_'. |
| renaming `$abc$509$g292' to `_602_'. |
| renaming `$abc$509$g293' to `_603_'. |
| renaming `$abc$509$g294' to `_604_'. |
| renaming `$abc$509$g295' to `_605_'. |
| renaming `$abc$509$g296' to `_606_'. |
| renaming `$abc$509$g297' to `_607_'. |
| renaming `$abc$509$g298' to `_608_'. |
| renaming `$abc$509$g299' to `_609_'. |
| renaming `$abc$509$g300' to `_610_'. |
| renaming `$abc$509$g301' to `_611_'. |
| renaming `$abc$509$g302' to `_612_'. |
| renaming `$abc$509$g303' to `_613_'. |
| renaming `$abc$509$g304' to `_614_'. |
| renaming `$abc$509$g305' to `_615_'. |
| renaming `$abc$509$g306' to `_616_'. |
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| renaming `$abc$509$g308' to `_618_'. |
| renaming `$abc$509$g309' to `_619_'. |
| renaming `$abc$509$g310' to `_620_'. |
| renaming `$abc$509$g311' to `_621_'. |
| renaming `$abc$509$g312' to `_622_'. |
| renaming `$abc$509$g313' to `_623_'. |
| renaming `$abc$509$g314' to `_624_'. |
| renaming `$abc$509$g315' to `_625_'. |
| renaming `$abc$509$g316' to `_626_'. |
| renaming `$abc$509$g317' to `_627_'. |
| renaming `$abc$509$g318' to `_628_'. |
| renaming `$abc$509$g319' to `_629_'. |
| renaming `$abc$509$g320' to `_630_'. |
| renaming `$abc$509$g321' to `_631_'. |
| renaming `$abc$509$g322' to `_632_'. |
| renaming `$abc$509$g323' to `_633_'. |
| renaming `$abc$509$g324' to `_634_'. |
| renaming `$abc$509$g325' to `_635_'. |
| renaming `$abc$509$g326' to `_636_'. |
| renaming `$abc$509$g327' to `_637_'. |
| renaming `$abc$509$g328' to `_638_'. |
| renaming `$abc$509$g329' to `_639_'. |
| renaming `$abc$509$g330' to `_640_'. |
| renaming `$abc$509$g331' to `_641_'. |
| renaming `$abc$509$g332' to `_642_'. |
| renaming `$abc$509$g333' to `_643_'. |
| renaming `$abc$509$g334' to `_644_'. |
| renaming `$abc$509$g335' to `_645_'. |
| renaming `$abc$509$g336' to `_646_'. |
| renaming `$abc$509$g337' to `_647_'. |
| renaming `$abc$509$g338' to `_648_'. |
| renaming `$abc$509$g339' to `_649_'. |
| renaming `$abc$509$g340' to `_650_'. |
| renaming `$abc$509$g341' to `_651_'. |
| renaming `$abc$509$g342' to `_652_'. |
| renaming `$abc$509$g343' to `_653_'. |
| renaming `$abc$509$g344' to `_654_'. |
| renaming `$abc$509$g345' to `_655_'. |
| renaming `$abc$509$g346' to `_656_'. |
| renaming `$abc$509$g347' to `_657_'. |
| renaming `$abc$509$g348' to `_658_'. |
| renaming `$abc$509$g349' to `_659_'. |
| renaming `$abc$509$g350' to `_660_'. |
| renaming `$abc$509$g351' to `_661_'. |
| renaming `$abc$509$g352' to `_662_'. |
| renaming `$abc$509$g353' to `_663_'. |
| renaming `$abc$509$g354' to `_664_'. |
| renaming `$abc$509$n143_1' to `_015_'. |
| renaming `$abc$509$n144' to `_016_'. |
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| renaming `$abc$509$n146_1' to `_018_'. |
| renaming `$abc$509$n147' to `_019_'. |
| renaming `$abc$509$n149_1' to `_020_'. |
| renaming `$abc$509$n151' to `_021_'. |
| renaming `$abc$509$n155' to `_022_'. |
| renaming `$abc$509$n156_1' to `_023_'. |
| renaming `$abc$509$n157' to `_024_'. |
| renaming `$abc$509$n158' to `_025_'. |
| renaming `$abc$509$n160' to `_026_'. |
| renaming `$abc$509$n162' to `_027_'. |
| renaming `$abc$509$n164' to `_028_'. |
| renaming `$abc$509$n166' to `_029_'. |
| renaming `$abc$509$n167' to `_030_'. |
| renaming `$abc$509$n169' to `_031_'. |
| renaming `$abc$509$n171' to `_032_'. |
| renaming `$abc$509$n173' to `_033_'. |
| renaming `$abc$509$n175' to `_034_'. |
| renaming `$abc$509$n176' to `_035_'. |
| renaming `$abc$509$n178' to `_036_'. |
| renaming `$abc$509$n180' to `_037_'. |
| renaming `$abc$509$n182_1' to `_038_'. |
| renaming `$abc$509$n184' to `_039_'. |
| renaming `$abc$509$n186' to `_040_'. |
| renaming `$abc$509$n188' to `_041_'. |
| renaming `$abc$509$n190' to `_042_'. |
| renaming `$abc$509$n192' to `_043_'. |
| renaming `$abc$509$n193_1' to `_044_'. |
| renaming `$abc$509$n194' to `_045_'. |
| renaming `$abc$509$n195_1' to `_046_'. |
| renaming `$abc$509$n196' to `_047_'. |
| renaming `$abc$509$n197_1' to `_048_'. |
| renaming `$abc$509$n198' to `_049_'. |
| renaming `$abc$509$n199' to `_050_'. |
| renaming `$abc$509$n200_1' to `_051_'. |
| renaming `$abc$509$n201' to `_052_'. |
| renaming `$abc$509$n203' to `_053_'. |
| renaming `$abc$509$n204_1' to `_054_'. |
| renaming `$abc$509$n205' to `_055_'. |
| renaming `$abc$509$n206_1' to `_056_'. |
| renaming `$abc$509$n207' to `_057_'. |
| renaming `$abc$509$n209' to `_058_'. |
| renaming `$abc$509$n210_1' to `_059_'. |
| renaming `$abc$509$n211' to `_060_'. |
| renaming `$abc$509$n212_1' to `_061_'. |
| renaming `$abc$509$n213' to `_062_'. |
| renaming `$abc$509$n214_1' to `_063_'. |
| renaming `$abc$509$n215' to `_064_'. |
| renaming `$abc$509$n216' to `_065_'. |
| renaming `$abc$509$n217' to `_066_'. |
| renaming `$abc$509$n218_1' to `_067_'. |
| renaming `$abc$509$n219' to `_068_'. |
| renaming `$abc$509$n220' to `_069_'. |
| renaming `$abc$509$n221' to `_070_'. |
| renaming `$abc$509$n222' to `_071_'. |
| renaming `$abc$509$n223_1' to `_072_'. |
| renaming `$abc$509$n224' to `_073_'. |
| renaming `$abc$509$n225_1' to `_074_'. |
| renaming `$abc$509$n226' to `_075_'. |
| renaming `$abc$509$n227_1' to `_076_'. |
| renaming `$abc$509$n228_1' to `_077_'. |
| renaming `$abc$509$n229' to `_078_'. |
| renaming `$abc$509$n230_1' to `_079_'. |
| renaming `$abc$509$n231' to `_080_'. |
| renaming `$abc$509$n232_1' to `_081_'. |
| renaming `$abc$509$n233_1' to `_082_'. |
| renaming `$abc$509$n234_1' to `_083_'. |
| renaming `$abc$509$n235' to `_084_'. |
| renaming `$abc$509$n236_1' to `_085_'. |
| renaming `$abc$509$n237' to `_086_'. |
| renaming `$abc$509$n238_1' to `_087_'. |
| renaming `$abc$509$n239' to `_088_'. |
| renaming `$abc$509$n240_1' to `_089_'. |
| renaming `$abc$509$n241' to `_090_'. |
| renaming `$abc$509$n242_1' to `_091_'. |
| renaming `$abc$509$n243' to `_092_'. |
| renaming `$abc$509$n244_1' to `_093_'. |
| renaming `$abc$509$n245' to `_094_'. |
| renaming `$abc$509$n246_1' to `_095_'. |
| renaming `$abc$509$n247' to `_096_'. |
| renaming `$abc$509$n248_1' to `_097_'. |
| renaming `$abc$509$n249' to `_098_'. |
| renaming `$abc$509$n250_1' to `_099_'. |
| renaming `$abc$509$n251' to `_100_'. |
| renaming `$abc$509$n252' to `_101_'. |
| renaming `$abc$509$n253' to `_102_'. |
| renaming `$abc$509$n254' to `_103_'. |
| renaming `$abc$509$n255' to `_104_'. |
| renaming `$abc$509$n256' to `_105_'. |
| renaming `$abc$509$n257' to `_106_'. |
| renaming `$abc$509$n258' to `_107_'. |
| renaming `$abc$509$n259' to `_108_'. |
| renaming `$abc$509$n260' to `_109_'. |
| renaming `$abc$509$n261' to `_110_'. |
| renaming `$abc$509$n262' to `_111_'. |
| renaming `$abc$509$n263' to `_112_'. |
| renaming `$abc$509$n264' to `_113_'. |
| renaming `$abc$509$n265' to `_114_'. |
| renaming `$abc$509$n266' to `_115_'. |
| renaming `$abc$509$n267' to `_116_'. |
| renaming `$abc$509$n271' to `_117_'. |
| renaming `$abc$509$n272' to `_118_'. |
| renaming `$abc$509$n273' to `_119_'. |
| renaming `$abc$509$n274' to `_120_'. |
| renaming `$abc$509$n275' to `_121_'. |
| renaming `$abc$509$n276' to `_122_'. |
| renaming `$abc$509$n277' to `_123_'. |
| renaming `$abc$509$n278' to `_124_'. |
| renaming `$abc$509$n279' to `_125_'. |
| renaming `$abc$509$n280' to `_126_'. |
| renaming `$abc$509$n281' to `_127_'. |
| renaming `$abc$509$n282' to `_128_'. |
| renaming `$abc$509$n283' to `_129_'. |
| renaming `$abc$509$n284' to `_130_'. |
| renaming `$abc$509$n285' to `_131_'. |
| renaming `$abc$509$n286' to `_132_'. |
| renaming `$abc$509$n288' to `_133_'. |
| renaming `$abc$509$n289_1' to `_134_'. |
| renaming `$abc$509$n290_1' to `_135_'. |
| renaming `$abc$509$n291' to `_136_'. |
| renaming `$abc$509$n292' to `_137_'. |
| renaming `$abc$509$n293' to `_138_'. |
| renaming `$abc$509$n294' to `_139_'. |
| renaming `$abc$509$n295' to `_140_'. |
| renaming `$abc$509$n296_1' to `_141_'. |
| renaming `$abc$509$n298_1' to `_142_'. |
| renaming `$abc$509$n299' to `_143_'. |
| renaming `$abc$509$n300_1' to `_144_'. |
| renaming `$abc$509$n302_1' to `_145_'. |
| renaming `$abc$509$n303' to `_146_'. |
| renaming `$abc$509$n305' to `_147_'. |
| renaming `$abc$509$n306_1' to `_148_'. |
| renaming `$abc$509$n307' to `_149_'. |
| renaming `$abc$509$n309' to `_150_'. |
| renaming `$abc$509$n310_1' to `_151_'. |
| renaming `$abc$509$n311' to `_152_'. |
| renaming `$abc$509$n312_1' to `_153_'. |
| renaming `$abc$509$n313' to `_154_'. |
| renaming `$abc$509$n314_1' to `_155_'. |
| renaming `$abc$509$n316' to `_156_'. |
| renaming `$abc$509$n317' to `_157_'. |
| renaming `$abc$509$n318' to `_158_'. |
| renaming `$abc$509$n320' to `_159_'. |
| renaming `$abc$509$n321' to `_160_'. |
| renaming `$abc$509$n322' to `_161_'. |
| renaming `$abc$509$n324' to `_162_'. |
| renaming `$abc$509$n325' to `_163_'. |
| renaming `$abc$509$n326' to `_164_'. |
| renaming `$abc$509$n328' to `_165_'. |
| renaming `$abc$509$n329' to `_166_'. |
| renaming `$abc$509$n330' to `_167_'. |
| renaming `$abc$509$n332' to `_168_'. |
| renaming `$abc$509$n333' to `_169_'. |
| renaming `$abc$509$n334' to `_170_'. |
| renaming `$abc$509$n336' to `_171_'. |
| renaming `$abc$509$n337' to `_172_'. |
| renaming `$abc$509$n338' to `_173_'. |
| renaming `$abc$509$n340' to `_174_'. |
| renaming `$abc$509$n341' to `_175_'. |
| renaming `$abc$509$n342' to `_176_'. |
| renaming `$abc$509$n343' to `_177_'. |
| renaming `$abc$509$n344_1' to `_178_'. |
| renaming `$abc$509$n345_1' to `_179_'. |
| renaming `$abc$509$n346_1' to `_180_'. |
| renaming `$abc$509$n348_1' to `_181_'. |
| renaming `$abc$509$n349_1' to `_182_'. |
| renaming `$abc$509$n350_1' to `_183_'. |
| renaming `$abc$509$n351_1' to `_184_'. |
| renaming `$abc$509$n352' to `_185_'. |
| renaming `$abc$509$n354' to `_186_'. |
| renaming `$abc$509$n355' to `_187_'. |
| renaming `$abc$509$n356' to `_188_'. |
| renaming `$abc$509$n357' to `_189_'. |
| renaming `$abc$509$n358' to `_190_'. |
| renaming `$abc$509$n359' to `_191_'. |
| renaming `$abc$509$n360' to `_192_'. |
| renaming `$abc$509$n363' to `_193_'. |
| renaming `$abc$509$n364' to `_194_'. |
| renaming `$abc$509$n365' to `_195_'. |
| renaming `$abc$509$n366' to `_196_'. |
| renaming `$abc$509$n368' to `_197_'. |
| renaming `$abc$509$n369' to `_198_'. |
| renaming `$abc$509$n370' to `_199_'. |
| renaming `$abc$509$n371' to `_200_'. |
| renaming `$abc$509$n372' to `_201_'. |
| renaming `$abc$509$n373' to `_202_'. |
| renaming `$abc$509$n374' to `_203_'. |
| renaming `$abc$509$n375' to `_204_'. |
| renaming `$abc$509$n376' to `_205_'. |
| renaming `$abc$509$n377' to `_206_'. |
| renaming `$abc$509$n378' to `_207_'. |
| renaming `$abc$509$n379' to `_208_'. |
| renaming `$abc$509$n380' to `_209_'. |
| renaming `$abc$509$n381' to `_210_'. |
| renaming `$abc$509$n383' to `_211_'. |
| renaming `$abc$509$n384' to `_212_'. |
| renaming `$abc$509$n385' to `_213_'. |
| renaming `$abc$509$n386' to `_214_'. |
| renaming `$abc$509$n387' to `_215_'. |
| renaming `$abc$509$n389' to `_216_'. |
| renaming `$abc$509$n390' to `_217_'. |
| renaming `$abc$509$n391' to `_218_'. |
| renaming `$abc$509$n392' to `_219_'. |
| renaming `$abc$509$n394' to `_220_'. |
| renaming `$abc$509$n395' to `_221_'. |
| renaming `$abc$509$n398' to `_222_'. |
| renaming `$abc$509$n399' to `_223_'. |
| renaming `$abc$509$n401' to `_224_'. |
| renaming `$abc$509$n403' to `_225_'. |
| renaming `$abc$509$n404' to `_226_'. |
| renaming `$abc$509$n405' to `_227_'. |
| renaming `$abc$509$n406' to `_228_'. |
| renaming `$abc$509$n407' to `_229_'. |
| renaming `$abc$509$n409' to `_230_'. |
| renaming `$abc$509$n410' to `_231_'. |
| renaming `$abc$509$n411' to `_232_'. |
| renaming `$abc$509$n412' to `_233_'. |
| renaming `$abc$509$n413' to `_234_'. |
| renaming `$abc$509$n415' to `_235_'. |
| renaming `$abc$509$n416' to `_236_'. |
| renaming `$abc$509$n417' to `_237_'. |
| renaming `$abc$509$n418' to `_238_'. |
| renaming `$abc$509$n419' to `_239_'. |
| renaming `$abc$509$n421' to `_240_'. |
| renaming `$abc$509$n422' to `_241_'. |
| renaming `$abc$509$n423' to `_242_'. |
| renaming `$abc$509$n424' to `_243_'. |
| renaming `$abc$509$n425' to `_244_'. |
| renaming `$abc$509$n427' to `_245_'. |
| renaming `$abc$509$n428' to `_246_'. |
| renaming `$abc$509$n429' to `_247_'. |
| renaming `$abc$509$n430' to `_248_'. |
| renaming `$abc$509$n431' to `_249_'. |
| renaming `$abc$509$n433' to `_250_'. |
| renaming `$abc$509$n434' to `_251_'. |
| renaming `$abc$509$n435' to `_252_'. |
| renaming `$abc$509$n436' to `_253_'. |
| renaming `$abc$509$n437' to `_254_'. |
| renaming `$abc$509$n439_1' to `_255_'. |
| renaming `$abc$509$n440' to `_256_'. |
| renaming `$abc$509$n441_1' to `_257_'. |
| renaming `$abc$509$n442' to `_258_'. |
| renaming `$abc$509$n443_1' to `_259_'. |
| renaming `$abc$509$n445_1' to `_260_'. |
| renaming `$abc$509$n446' to `_261_'. |
| renaming `$abc$509$n447_1' to `_262_'. |
| renaming `$abc$509$n448' to `_263_'. |
| renaming `$abc$509$n449_1' to `_264_'. |
| renaming `$abc$509$n451_1' to `_265_'. |
| renaming `$abc$509$n453_1' to `_266_'. |
| renaming `$abc$509$n454' to `_267_'. |
| renaming `$abc$509$n455' to `_268_'. |
| renaming `$abc$509$n456' to `_269_'. |
| renaming `$abc$509$n458' to `_270_'. |
| renaming `$abc$509$n459' to `_271_'. |
| renaming `$abc$509$n460' to `_272_'. |
| renaming `$abc$509$n463' to `_273_'. |
| renaming `$abc$509$n464' to `_274_'. |
| renaming `$abc$509$n465' to `_275_'. |
| renaming `$abc$509$n466' to `_276_'. |
| renaming `$abc$509$n467' to `_277_'. |
| renaming `$abc$509$n469' to `_278_'. |
| renaming `$abc$509$n470' to `_279_'. |
| renaming `$abc$509$n471' to `_280_'. |
| renaming `$abc$509$n472' to `_281_'. |
| renaming `$abc$509$n473' to `_282_'. |
| renaming `$abc$509$n475' to `_283_'. |
| renaming `$abc$509$n476' to `_284_'. |
| renaming `$abc$509$n477' to `_285_'. |
| renaming `$abc$509$n478' to `_286_'. |
| renaming `$abc$509$n479' to `_287_'. |
| renaming `$abc$509$n481' to `_288_'. |
| renaming `$abc$509$n482' to `_289_'. |
| renaming `$abc$509$n483' to `_290_'. |
| renaming `$abc$509$n484' to `_291_'. |
| renaming `$abc$509$n485' to `_292_'. |
| renaming `$abc$509$n487' to `_293_'. |
| renaming `$abc$509$n488' to `_294_'. |
| renaming `$abc$509$n489' to `_295_'. |
| renaming `$abc$509$n491' to `_296_'. |
| renaming `$abc$509$n492' to `_297_'. |
| renaming `$abc$509$n493' to `_298_'. |
| renaming `$abc$509$n495' to `_299_'. |
| renaming `$abc$509$n496' to `_300_'. |
| renaming `$abc$509$n497' to `_301_'. |
| renaming `$abc$509$n498' to `_302_'. |
| renaming `$abc$509$n499' to `_303_'. |
| renaming `$abc$509$n501' to `_304_'. |
| renaming `$abc$509$n502' to `_305_'. |
| renaming `$abc$509$n503' to `_306_'. |
| renaming `$abc$509$n504' to `_307_'. |
| renaming `$abc$509$n505' to `_308_'. |
| renaming `$not$rtl/simple_spi_top.v:182$46.Y' to `_309_'. |
| renaming `$procdff$345.V[0].P.PN.PN0.ff' to `_665_'. |
| renaming `$procdff$345.V[1].P.PN.PN0.ff' to `_666_'. |
| renaming `$procdff$345.V[2].P.PN.PN0.ff' to `_667_'. |
| renaming `$procdff$345.V[3].P.PN.PN0.ff' to `_668_'. |
| renaming `$procdff$345.V[4].P.PN.PN1.ff' to `_669_'. |
| renaming `$procdff$345.V[5].P.PN.PN0.ff' to `_670_'. |
| renaming `$procdff$345.V[6].P.PN.PN0.ff' to `_671_'. |
| renaming `$procdff$345.V[7].P.PN.PN0.ff' to `_672_'. |
| renaming `$procdff$346.V[0].P.PN.PN0.ff' to `_673_'. |
| renaming `$procdff$346.V[1].P.PN.PN0.ff' to `_674_'. |
| renaming `$procdff$346.V[2].P.PN.PN0.ff' to `_675_'. |
| renaming `$procdff$346.V[3].P.PN.PN0.ff' to `_676_'. |
| renaming `$procdff$346.V[4].P.PN.PN0.ff' to `_677_'. |
| renaming `$procdff$346.V[5].P.PN.PN0.ff' to `_678_'. |
| renaming `$procdff$346.V[6].P.PN.PN0.ff' to `_679_'. |
| renaming `$procdff$346.V[7].P.PN.PN0.ff' to `_680_'. |
| renaming `$procdff$347.V[0].ff' to `_681_'. |
| renaming `$procdff$347.V[1].ff' to `_682_'. |
| renaming `$procdff$347.V[2].ff' to `_683_'. |
| renaming `$procdff$347.V[3].ff' to `_684_'. |
| renaming `$procdff$347.V[4].ff' to `_685_'. |
| renaming `$procdff$347.V[5].ff' to `_686_'. |
| renaming `$procdff$347.V[6].ff' to `_687_'. |
| renaming `$procdff$347.V[7].ff' to `_688_'. |
| renaming `$procdff$348.V[0].P.PN.PN0.ff' to `_689_'. |
| renaming `$procdff$349.V[0].ff' to `_690_'. |
| renaming `$procdff$350.V[0].ff' to `_691_'. |
| renaming `$procdff$351.V[0].ff' to `_692_'. |
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| renaming `$procdff$352.V[11].ff' to `_695_'. |
| renaming `$procdff$352.V[1].ff' to `_696_'. |
| renaming `$procdff$352.V[2].ff' to `_697_'. |
| renaming `$procdff$352.V[3].ff' to `_698_'. |
| renaming `$procdff$352.V[4].ff' to `_699_'. |
| renaming `$procdff$352.V[5].ff' to `_700_'. |
| renaming `$procdff$352.V[6].ff' to `_701_'. |
| renaming `$procdff$352.V[7].ff' to `_702_'. |
| renaming `$procdff$352.V[8].ff' to `_703_'. |
| renaming `$procdff$352.V[9].ff' to `_704_'. |
| renaming `$procdff$353.V[0].ff' to `_705_'. |
| renaming `$procdff$353.V[1].ff' to `_706_'. |
| renaming `$procdff$353.V[2].ff' to `_707_'. |
| renaming `$procdff$354.V[0].ff' to `_708_'. |
| renaming `$procdff$355.V[0].ff' to `_709_'. |
| renaming `$procdff$356.V[0].ff' to `_710_'. |
| renaming `$procdff$356.V[1].ff' to `_711_'. |
| renaming `$procdff$357.V[0].ff' to `_712_'. |
| renaming `$procdff$357.V[1].ff' to `_713_'. |
| renaming `$procdff$357.V[2].ff' to `_714_'. |
| renaming `$procdff$357.V[3].ff' to `_715_'. |
| renaming `$procdff$357.V[4].ff' to `_716_'. |
| renaming `$procdff$357.V[5].ff' to `_717_'. |
| renaming `$procdff$357.V[6].ff' to `_718_'. |
| renaming `$procdff$357.V[7].ff' to `_719_'. |
| renaming `$procdff$358.V[0].ff' to `_720_'. |
| renaming `$procdff$359.V[0].ff' to `_721_'. |
| renaming `$procdff$359.V[1].ff' to `_722_'. |
| |
| READY. |
