blob: bb01bd46b643076045417529a117d78fb3adc758 [file] [log] [blame]
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* SURELOG System Verilog Compiler/Linter *
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Copyright (c) 2017-2019 ACE Cloud,
Authorized used only.
VERSION: 0.05
BUILT : Nov 3 2019
DATE : 2019-11-03.21:43:17
COMMAND: -writepp -parse -mt max -nopython -fileunit cache/synth.v rtl/aes.v rtl/byte_mixcolum.v rtl/keysched.v rtl/mixcolum.v rtl/sbox.v rtl/subbytes.v rtl/timescale.v rtl/word_mixcolum.v +incdir+. -nobuiltin -nocache
[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
[INFO :CM0024] Executing with 4 threads.
[INFO :CM0020] Separate compilation-unit mode is on.
[WARNI:PA0205] cache/synth.v:1 No timescale set for "aes".
[WARNI:PA0205] cache/synth.v:6759 No timescale set for "byte_mixcolum".
[WARNI:PA0205] cache/synth.v:6906 No timescale set for "keysched".
[WARNI:PA0205] cache/synth.v:9037 No timescale set for "mixcolum".
[WARNI:PA0205] cache/synth.v:12017 No timescale set for "sbox".
[WARNI:PA0205] cache/synth.v:12581 No timescale set for "subbytes".
[WARNI:PA0205] cache/synth.v:15275 No timescale set for "word_mixcolum".
[INFO :CP0300] Compilation...
[INFO :CP0303] cache/synth.v:6759 Compile module "work@byte_mixcolum".
[INFO :CP0303] cache/synth.v:1 Compile module "work@aes".
[INFO :CP0303] cache/synth.v:6906 Compile module "work@keysched".
[INFO :CP0303] cache/synth.v:9037 Compile module "work@mixcolum".
[INFO :CP0303] cache/synth.v:12581 Compile module "work@subbytes".
[INFO :CP0303] cache/synth.v:15275 Compile module "work@word_mixcolum".
[INFO :CP0303] cache/synth.v:12017 Compile module "work@sbox".
[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "data_o".
[NOTE :CP0309] cache/synth.v:12017 Implicit port type (wire) for "data_o".
[NOTE :CP0309] cache/synth.v:6759 Implicit port type (wire) for "outx",
there are 1 more instances of this message.
[NOTE :CP0309] cache/synth.v:12581 Implicit port type (wire) for "sbox_data_o",
there are 1 more instances of this message.
[NOTE :CP0309] cache/synth.v:6906 Implicit port type (wire) for "new_key_o",
there are 3 more instances of this message.
[NOTE :CP0309] cache/synth.v:15275 Implicit port type (wire) for "outx",
there are 1 more instances of this message.
[INFO :EL0526] Design Elaboration...
[NOTE :EL0503] cache/synth.v:1 Top level module "work@aes".
[NOTE :EL0508] Nb Top level modules: 1.
[NOTE :EL0509] Max instance depth: 4.
[NOTE :EL0510] Nb instances: 10.
[NOTE :EL0511] Nb leaf instances: 7.
[ FATAL] : 0
[ ERROR] : 0
[WARNING] : 7
[ NOTE] : 11
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* End SURELOG SVerilog Compiler/Linter *
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