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| * SURELOG System Verilog Compiler/Linter * |
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| Copyright (c) 2017-2019 ACE Cloud, |
| Authorized used only. |
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| VERSION: 0.05 |
| BUILT : Nov 3 2019 |
| DATE : 2019-11-03.21:43:17 |
| COMMAND: -writepp -parse -mt max -nopython -fileunit cache/synth.v rtl/aes.v rtl/byte_mixcolum.v rtl/keysched.v rtl/mixcolum.v rtl/sbox.v rtl/subbytes.v rtl/timescale.v rtl/word_mixcolum.v +incdir+. -nobuiltin -nocache |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [WARNI:PA0205] cache/synth.v:1 No timescale set for "aes". |
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| [WARNI:PA0205] cache/synth.v:6759 No timescale set for "byte_mixcolum". |
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| [WARNI:PA0205] cache/synth.v:6906 No timescale set for "keysched". |
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| [WARNI:PA0205] cache/synth.v:9037 No timescale set for "mixcolum". |
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| [WARNI:PA0205] cache/synth.v:12017 No timescale set for "sbox". |
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| [WARNI:PA0205] cache/synth.v:12581 No timescale set for "subbytes". |
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| [WARNI:PA0205] cache/synth.v:15275 No timescale set for "word_mixcolum". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:6759 Compile module "work@byte_mixcolum". |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@aes". |
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| [INFO :CP0303] cache/synth.v:6906 Compile module "work@keysched". |
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| [INFO :CP0303] cache/synth.v:9037 Compile module "work@mixcolum". |
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| [INFO :CP0303] cache/synth.v:12581 Compile module "work@subbytes". |
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| [INFO :CP0303] cache/synth.v:15275 Compile module "work@word_mixcolum". |
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| [INFO :CP0303] cache/synth.v:12017 Compile module "work@sbox". |
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| [NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "data_o". |
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| [NOTE :CP0309] cache/synth.v:12017 Implicit port type (wire) for "data_o". |
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| [NOTE :CP0309] cache/synth.v:6759 Implicit port type (wire) for "outx", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] cache/synth.v:12581 Implicit port type (wire) for "sbox_data_o", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] cache/synth.v:6906 Implicit port type (wire) for "new_key_o", |
| there are 3 more instances of this message. |
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| [NOTE :CP0309] cache/synth.v:15275 Implicit port type (wire) for "outx", |
| there are 1 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] cache/synth.v:1 Top level module "work@aes". |
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| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 4. |
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| [NOTE :EL0510] Nb instances: 10. |
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| [NOTE :EL0511] Nb leaf instances: 7. |
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| [ FATAL] : 0 |
| [ ERROR] : 0 |
| [WARNING] : 7 |
| [ NOTE] : 11 |
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| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
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