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foss-fpga-tools
/
third_party
/
Surelog
/
36edd2bd845c2e56e36b75d2696ae7a98914e2a8
/
.
/
SVIncCompil
/
Testcases
/
YosysTestSuite
/
errors
/
syntax_err09.v
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module
a
(
input wire x
=
1
'b0);
endmodule
