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36edd2bd845c2e56e36b75d2696ae7a98914e2a8
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SVIncCompil
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Testcases
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YosysTests
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architecture
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xilinx_srl_minlen.ys
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read_verilog
../
top
.
v
synth_xilinx
xilinx_srl
-
fixed
-
minlen
1
design
-
reset
read_verilog
../
top
.
v
synth_xilinx
write_verilog synth
.
v
