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Surelog
/
36edd2bd845c2e56e36b75d2696ae7a98914e2a8
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01023
/
top.v
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module
mux_case_5_1
(
i
,
s
,
o
);
input
[
4
:
0
]
i
;
output o
;
input
[
2
:
0
]
s
;
\$shiftx
#(
.
A_SIGNED
(
32
'd0),
.A_WIDTH(32'
d1
),
.
B_SIGNED
(
32
'd0),
.B_WIDTH(32'
sd0
),
.
Y_WIDTH
(
32
'd1)
) _34_ (
.A(i[4]),
.B(),
.Y(o)
);
endmodule