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foss-fpga-tools
/
third_party
/
Surelog
/
36edd2bd845c2e56e36b75d2696ae7a98914e2a8
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01364
/
top.v
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module
top
();
wire o
;
wire a
;
wire b
;
wire
[
3
:
0
]
i
;
assign o
=
i
==
4
'hb ? a:b;
endmodule
