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foss-fpga-tools
/
third_party
/
Surelog
/
36edd2bd845c2e56e36b75d2696ae7a98914e2a8
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
full_adder
/
top.v
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module
top
(
input x
,
input y
,
input cin
,
output A
,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`
else
assign
{
cout
,
A
}
=
cin
-
y
*
x
;
`endif
endmodule