SVIncCompil/Testcases/ApbSlave/ApbSlave_diff.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_all/surelog.log.

[NOTE :CM0009] Command line argument "+vcs+flush+all" ignored.

[NOTE :CM0009] Command line argument "+warn=all" ignored.

[WARNI:CM0010] Command line argument "-sverilog" ignored.

[INFO :CM0024] Executing with 4 threads.

[INFO :PP0122] Preprocessing source file "/home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv".

[INFO :PP0122] Preprocessing source file "../../../UVM/svunit_base/svunit_pkg.sv".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_defines.svh".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_types.svh".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_base.sv".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_testcase.sv".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_testsuite.sv".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_testrunner.sv".

[INFO :PP0123] Preprocessing include file "../../../UVM/svunit_base/svunit_globals.svh".

[INFO :PP0122] Preprocessing source file "design.sv".

[INFO :PP0122] Preprocessing source file "testbench.sv".

[INFO :PA0201] Parsing source file "../../../UVM/svunit_base/svunit_pkg.sv".

[INFO :PA0201] Parsing source file "../../../UVM/svunit_base/svunit_pkg.sv".

[INFO :PA0201] Parsing source file "/home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv".

[INFO :PA0201] Parsing source file "../../../UVM/svunit_base/svunit_pkg.sv".

[INFO :PA0201] Parsing source file "design.sv".

[INFO :PA0201] Parsing source file "testbench.sv".

[INFO :PA0201] Parsing source file "../../../UVM/svunit_base/svunit_pkg.sv".

[INFO :CM0029] Using global timescale: "1ns/1ns".

[INFO :CP0300] Compilation...

[INFO :CP0301] ../../../UVM/svunit_base/svunit_pkg.sv:23 Compile package "svunit_pkg".

[INFO :CP0303] testbench.sv:5 Compile module "work@apb_slave_unit_test".

[INFO :CP0303] design.sv:2 Compile module "work@apb_slave".

[INFO :CP0302] ../../../UVM/svunit_base/svunit_testcase.sv:26 Compile class "svunit_pkg::svunit_testcase".

[INFO :CP0302] ../../../UVM/svunit_base/svunit_testrunner.sv:26 Compile class "svunit_pkg::svunit_testrunner".

[INFO :CP0302] ../../../UVM/svunit_base/svunit_base.sv:26 Compile class "svunit_pkg::svunit_base".

[INFO :CP0302] ../../../UVM/svunit_base/svunit_testsuite.sv:26 Compile class "svunit_pkg::svunit_testsuite".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] testbench.sv:5 Top level module "work@apb_slave_unit_test".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 2.

[NOTE :EL0511] Nb leaf instances: 0.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 1
[   NOTE] : 7

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*   End SURELOG SVerilog Compiler/Linter   *
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3.98user 0.05system 0:01.83elapsed 220%CPU (0avgtext+0avgdata 82344maxresident)k
0inputs+816outputs (0major+22943minor)pagefaults 0swaps