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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
Icarus
/
ivltests
/
pr547.v
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module
top
;
reg
[
9
:
0
]
a
;
reg b
;
initial
begin
a
=
10
'h3ff;
b = a[15];
$display("A = %h, b = %b", a, b);
end // initial begin
endmodule // top