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foss-fpga-tools
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third_party
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Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
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.
/
SVIncCompil
/
Testcases
/
YosysBigSim
/
reed_solomon_decoder
/
sim
/
settings.sh
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TOP
=
"RS_dec"
RTL
=
"BM_lamda.v DP_RAM.v error_correction.v GF_matrix_ascending_binary.v
GF_matrix_dec.v GF_mult_add_syndromes.v input_syndromes.v
lamda_roots.v Omega_Phy.v out_stage.v RS_dec.v transport_in2out.v"
SIM
=
"RS_dec_tb.v"
