| read_verilog ../latches.v | |
| proc | |
| hierarchy -top latches | |
| flatten | |
| synth_xilinx | |
| #Vivado synthesizes 1 BUFG, 8 LDCE. | |
| select -assert-count 2 t:LUT2 | |
| select -assert-count 1 t:$_DLATCH_P_ | |
| #ERROR: Assertion failed: selection is not empty: t:LUT2 t:$_DLATCH_P_ %% t:* %D | |
| #select -assert-none t:LUT2 t:$_DLATCH_P_ %% t:* %D |