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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
frontends
/
read_aiger
/
top.v
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module
top
(
input x
,
input y
,
input cin
,
input clk
,
output A
,
output cout
);
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
`
else
assign
{
cout
,
A
}
=
cin
-
y
*
x
;
`endif
endmodule