blob: f30f9ded8a699e18a9b07778a7d01553644c8704 [file] [log] [blame]
read_verilog -sv ../top.v
aigmap
write_aiger -ascii aiger.aiger
design -reset
read_aiger aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v