blob: a04a9242c611a77db0ba181408c7a94de3fcfb44 [file] [log] [blame]
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -clk_name clk aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v