blob: c87e7fe80fd8116a2b4c40916f4d332011fa0727 [file] [log] [blame]
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -overwrite ilang.ilang
dump -n -o file1.il
write_verilog synth.v