Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
design_import.ys
blob: 9d3f46ec3857f3b152a4eb4b10579a84713a4e0d [
file
] [
log
] [
blame
]
read_verilog
-
sv
../
top
.
v
proc
design
-
save first
tee
-
o result
.
log design
-
import
first top
