blob: 687bceadb271fd17c7cadeecd5c0f12b30b05bde [file] [log] [blame]
read_verilog ../top.v
tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
tee -o result.log dump