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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
mutate_const0.ys
blob: 9f33ece6fb8affbdf2567021936f54bd2704bea4 [
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read_verilog
../
top
.
v
tee
-
o result
.
log mutate
-
mode const0
-
module
top
-
cell $add$
../
top
.
v
:
12
$2
-
port Y
-
portbit
0
-
wire A
-
wirebit
0
-
src
../
top
.
v
:
7
-
src
../
top
.
v
:
12
tee
-
o result
.
log
dump
