Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
mutate_inv.ys
blob: 1dc0a5fadc649d00ecf382f6ad74dfe0385a3c8d [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
tee
-
o result
.
log mutate
-
mode inv
-
module
top
-
cell $add$
../
top
.
v
:
12
$2
-
port Y
-
portbit
0
-
wire A
-
wirebit
0
-
src
../
top
.
v
:
7
-
src
../
top
.
v
:
12
tee
-
o result
.
log
dump
