Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
sat_prove.ys
blob: f79c3113018f61eb6c539602f54e28fcef8b7e99 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
tee
-
o result
.
log sat
-
ignore_unknown_cells
-
prove x
1
top
