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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00287
/
top.v
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module
top
(
input
[
6
:
0
]
D
,
input
[
1
:
0
]
S
,
output reg
[
1
:
0
]
Y
);
always
@*
begin
:
block
reg
[
3
:
0
]
data
[
0
:
3
];
data
[
0
]
=
D
[
3
:
0
];
data
[
1
]
=
D
[
4
:
1
];
data
[
2
]
=
D
[
5
:
2
];
data
[
3
]
=
D
[
6
:
3
];
Y
=
data
[
S
];
end
endmodule
