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3f4e38faba84ce292e5f05601b70dd598f686411
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SVIncCompil
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Testcases
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YosysTests
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regression
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scripts
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issue_00171.ys
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read_verilog
../
top
.
v
proc
;
opt
;
fsm
;
opt
;
memory
;
opt
;
techmap
;
opt
scc
-
all_cell_types
#and then put each found SCC into a module using submod.
scc
-
all_cell_types
synth
-
top top
write_verilog synth
.
v
