SVIncCompil/Testcases/YosysTests/regression/scripts/issue_00175.ys - third_party/Surelog - Git at Google

 read_verilog ../top.v
 hierarchy
 proc
 opt
 memory
 opt
 fsm
 setundef -zero
 opt -full -fine
 setundef -zero
 opt -full -fine
 synth -top top
 write_verilog synth.v
	read_verilog ../top.v
	hierarchy
	proc
	opt
	memory
	opt
	fsm
	setundef -zero
	opt -full -fine
	setundef -zero
	opt -full -fine
	synth -top top
	write_verilog synth.v