blob: 67b815d838d8ac3afd9115d43954d570f507df29 [file] [log] [blame]
read_verilog -lib +/ice40/cells_sim.v
read_verilog ../top.v
hierarchy -top main
proc
flatten
opt_expr
opt_clean
opt
wreduce
alumacc
share -aggressive -force
opt
fsm
opt -fast
write_ilang dump.ilang
synth -top main
write_verilog synth.v