| read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v | |
| tee -o result.log synth_ecp5 -blif foo.blif |