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foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
expose_input.ys
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read_verilog
../
top
.
v
synth
-
top top
expose
-
input
proc
flatten
opt
opt_rmdff
expose
-
input
design
-
reset
read_verilog
../
top
.
v
synth
-
top top
write_verilog synth
.
v
