Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_map_design.ys
blob: f6fef20e4ed85d9955a0e44e8577ac7c452d4d59 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
design
-
save top_test
extract
-
map
%
top_test
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v