Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_verbose.ys
blob: 62601856397097c0e74483271f379f7197a77025 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
extract
-
map
../
top
.
v
-
verbose
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v
