Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
ice40_dsp.ys
blob: 542fe5ac2bcd5692f63dd4fbbc071685e8b54e2c [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
proc
ice40_dsp
tee
-
o result
.
log
dump
synth_ice40
-
top top
design
-
reset
read_verilog
../
top
.
v
synth
-
top top
write_verilog synth
.
v