Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
3f4e38faba84ce292e5f05601b70dd598f686411
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
opt_lut_limit.ys
blob: b2f6bfe25854ff9c73de2346877dbc132d4c26c2 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
synth_ice40
opt_lut
-
limit
2
design
-
reset
read_verilog
../
top
.
v
synth
-
top top
write_verilog synth
.
v
